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MC92600UM/D 3/2003 REV 2
MC92600 Quad 1.25 Gbaud SERDES User's Manual
Devices Supported: MC92600CJUB MC92600JUB MC92600ZTB
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: (800) 521-6274 HOME PAGE: www.motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2003
Introduction
Transmitter Receiver System Design Considerations Test Features Electrical Specifications and Characteristics Package Description
1 2 3 4 5 6 7
Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index
A B GLO IND
1 2 3 4 5 6 7
Introduction
Transmitter Receiver System Design Considerations Test Features Electrical Specifications and Characteristics Package Description
A B GLO IND
Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index
Contents
Paragraph Section Number Title About This Book Audience ................................................................................................................ xi Organization........................................................................................................... xi Suggested Reading................................................................................................ xii General Information...................................................................................... xii Related Documentation ................................................................................ xii Conventions ......................................................................................................... xiii Signals.................................................................................................................. xiii Chapter 1 Introduction 1.1 1.2 1.3 1.4 1.5 Overview.............................................................................................................. 1-1 Features ................................................................................................................ 1-1 Block Diagram ..................................................................................................... 1-2 References............................................................................................................ 1-4 Revision History .................................................................................................. 1-4 Chapter 2 Transmitter 2.1 2.2 2.3 2.3.1 2.3.2 2.4 2.4.1 2.4.2 2.5 2.5.1 2.5.2 2.5.3 Transmitter Block Diagram ................................................................................. 2-2 Transmitter Interface Signals ............................................................................... 2-2 Transmission Modes ............................................................................................ 2-4 Double Data Rate Mode .................................................................................. 2-4 Repeater Mode................................................................................................. 2-4 Types of Transmission Data................................................................................. 2-5 Transmitting Uncoded Data ............................................................................. 2-5 Transmitting Coded Data ................................................................................. 2-6 Device Operations................................................................................................ 2-7 8B/10B Encoder Operation.............................................................................. 2-7 Transmit Driver Operation............................................................................... 2-7 Transmit Data Input Register Operation.......................................................... 2-8 Page Number
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Contents
Paragraph Number Title Chapter 3 Receiver 3.1 3.2 3.3 3.3.1 3.3.1.1 3.3.1.2 3.3.1.3 3.3.2 3.3.2.1 3.3.2.2 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.4.1 3.5.4.2 3.5.4.3 3.5.4.4 3.5.4.5 3.6 Receiver Block Diagram...................................................................................... 3-2 Receiver Interface Signals.................................................................................... 3-2 Alignment Modes................................................................................................. 3-4 Byte Alignment ................................................................................................ 3-5 Byte-Aligned with Realignment .................................................................. 3-5 Byte-Aligned with Idle Realignment and Disparity Word Alignment......... 3-6 Non-Aligned ................................................................................................ 3-6 Word Alignment............................................................................................... 3-6 Word Synchronization Method.................................................................... 3-7 Word Synchronization Recommended Settings .......................................... 3-8 Receiver Clock Timing Modes ............................................................................ 3-8 Recovered Clock Timing Mode ....................................................................... 3-9 Reference Clock Timing Mode........................................................................ 3-9 Device Operations.............................................................................................. 3-10 Receiver Input Amplifier................................................................................ 3-10 8B/10B Decoder Operation ........................................................................... 3-11 Transition Tracking Loop and Data Recovery ............................................... 3-11 Receiver Interface Modes .............................................................................. 3-12 Byte Interface Mode .................................................................................. 3-12 10-Bit Interface Mode................................................................................ 3-13 Double Data Rate Mode ............................................................................ 3-13 Half-Speed Mode....................................................................................... 3-13 Repeater Mode........................................................................................... 3-13 Receiver Interface Error Codes.......................................................................... 3-14 Chapter 4 System Design Considerations 4.1 4.2 4.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.5
iv
Page Number
Reference Clock Configuration............................................................................ 4-1 Start-up................................................................................................................. 4-1 Standby Mode ...................................................................................................... 4-3 Repeater Mode ..................................................................................................... 4-3 10-Bit Interface Mode...................................................................................... 4-4 Byte Alignment Mode...................................................................................... 4-4 Word Synchronization Mode ........................................................................... 4-4 Recovered Clock Mode.................................................................................... 4-5 Add/Drop Idle Mode........................................................................................ 4-5 Half-Speed Mode, Double Data Rate Mode.................................................... 4-5 Configuration and Control Signals....................................................................... 4-5
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Contents
Paragraph Number 4.6 4.7 4.8 Title Page Number
Power Supply Requirements................................................................................ 4-6 Phase-Locked Loop (PLL) Power Supply Filtering ............................................ 4-6 Decoupling Recommendations ............................................................................ 4-7 Chapter 5 Test Features
5.1 5.2 5.3 5.4
Loop Back System Test........................................................................................ 5-1 BIST Sequence System Test Mode...................................................................... 5-2 Loop Back BIST Sequence System Test Mode ................................................... 5-3 Board Level Manufacturing Test Mode ............................................................... 5-3 Chapter 6 Electrical Specifications and Characteristics
6.1 6.1.1 6.2 6.2.1 6.3 6.3.1 6.3.1.1 6.3.1.2 6.3.1.3 6.3.1.4 6.3.1.5 6.3.1.6 6.3.2 6.3.3 6.3.4 6.3.4.1 6.3.4.2
General Characteristics ........................................................................................ 6-1 General Parameters .......................................................................................... 6-1 DC Electrical Characteristics............................................................................... 6-1 Characteristics of the 3.3V Device .................................................................. 6-3 AC Electrical Characteristics ............................................................................... 6-4 Parallel Port Interface Timing.......................................................................... 6-4 Transmitter (DDRE = Low)....................................................................... 6-5 Transmitter (DDRE = High) ...................................................................... 6-5 Receiver (DDRE = Low, RCCE = Low).................................................. 6-5 Reciever (DDRE = High, RCCE = Low)................................................. 6-6 Receiver (DDRE = Low, RCCE = High)................................................. 6-7 Receiver (DDRE = High, RCCE = High)................................................ 6-7 Reference Clock Timing .................................................................................. 6-8 Receiver Recovered Clock Timing .................................................................. 6-9 Serial Data Link Timing ................................................................................ 6-10 Link Differential Output ............................................................................ 6-10 Link Differential Input............................................................................... 6-11 Chapter 7 Package Description
7.1 7.2 7.3 7.4 7.5 7.6
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196 MAPBGA Package Parameter Summary ..................................................... 7-1 217 PBGA Package Parameter Summary............................................................ 7-1 Nomenclature and Dimensions of the 196 MAPBGA Package .......................... 7-1 Nomenclature and Dimensions of the 217 MAPBGA Package .......................... 7-4 Package Thermal Characteristics ......................................................................... 7-8 MC92600 Chip Pinout Listing............................................................................. 7-8
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Contents
Paragraph Number Title Appendix A Ordering Information Appendix B 8B/10B Coding Scheme B.1 B.1.1 B.1.2 B.1.3 B.2 Overview..............................................................................................................B-1 Naming Transmission Characters ....................................................................B-2 Encoding ..........................................................................................................B-2 Calculating Running Disparity ........................................................................B-3 Data Tables...........................................................................................................B-3 Glossary of Terms and Abbreviations Index Page Number
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Figures
Figure Number 1-1 2-1 3-1 4-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 7-1 7-2 7-3 7-4 7-5 7-6 A-1 B-1 B-2 B-3 Title Page Number
MC92600 Block Diagram ........................................................................................... 1-3 MC92600 Transmitter Block Diagram ....................................................................... 2-2 Receiver Block Diagram ............................................................................................. 3-2 PLL Power Supply Filter Circuit ................................................................................ 4-7 Transmitter Interface Timing Diagram (DDRE = Low) ........................................... 6-5 Transmitter Interface Timing Diagram (DDRE = High)........................................... 6-5 Receiver Interface Timing Diagram (DDRE = Low, RCCE = Low) ...................... 6-6 Receiver Interface Timing Diagram (DDRE = High, RCCE = Low) ..................... 6-6 Receiver Interface Timing Diagram (DDRE = Low, RCCE = High....................... 6-7 Receiver Interface Timing Diagram (DDRE = High, RCCE = High) .................... 6-8 Reference Clock Timing Diagram .............................................................................. 6-8 Recovered Clock Timing Diagram.............................................................................. 6-9 Link Differential Output Timing Diagram ................................................................ 6-10 Link Differential Input Timing Diagram................................................................... 6-11 196 MAPBGA Nomenclature ..................................................................................... 7-2 196 MAPBGA Dimensions ........................................................................................ 7-3 196 MAPBGA Package .............................................................................................. 7-4 217 PBGA Nomenclature ........................................................................................... 7-5 217 PBGA Dimensions ............................................................................................... 7-6 217 PBGA Package..................................................................................................... 7-7 Motorola Part Number Key........................................................................................ A-1 Unencoded Transmission Character Bit Ordering ......................................................B-1 Encoded Transmission Character Bit Ordering ..........................................................B-2 Character Transmission...............................................................................................B-3
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Figures
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Figures
Figure Number Title Page Number
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Tables
Table Number 1-1 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-9 6-8 6-10 6-11 6-12 6-13 6-14 7-1 7-2 B-1 B-2 B-3 Title Page Number
Revision History Table................................................................................................ 1-4 MC92600 Transmitter Interface Signals ..................................................................... 2-3 Transmitter Control States .......................................................................................... 2-5 MC92600 Receiver Interface Signals ......................................................................... 3-3 Byte Alignment Modes ............................................................................................... 3-5 Word Synchronization Events..................................................................................... 3-7 Word Synchronization Settings................................................................................... 3-8 Receiver Interface Error Codes (Byte Interface)....................................................... 3-14 Receiver Interface Error Codes (10-Bit Interface) .................................................... 3-14 Legal Reference Clock Frequency Ranges ................................................................. 4-1 Start-up Sequence Step Duration ................................................................................ 4-2 Settings for Repeater Mode......................................................................................... 4-3 Asynchronous Configuration and Control Signals...................................................... 4-6 Test Mode State Selection........................................................................................... 5-1 BIST Error Codes........................................................................................................ 5-3 Absolute Maximum Ratings ....................................................................................... 6-2 Recommended Operating Conditions ......................................................................... 6-2 DC Electrical Specifications for 3.3V Power Supply ................................................. 6-3 DC Electrical Specifications for 2.5V Power Supply ................................................. 6-4 Transmitter Timing Specification (DDRE = Low).................................................... 6-5 Transmitter Timing Specification (DDRE = High) ................................................... 6-5 Receiver Timing Specification (DDRE = Low, RCCE = Low) .............................. 6-6 Receiver Timing Specification (DDRE = Low, RCCE = High).............................. 6-7 Receiver Timing Specification (DDRE = High, RCCE = Low............................... 6-7 Receiver Timing Specification (DDRE = High, RCCE = High)......................... 6-8 Reference Clock Specification .................................................................................... 6-8 Recovered Clock Specification ................................................................................. 6-10 Link Differential Output Specification...................................................................... 6-10 Link Differential Input Timing Specification............................................................ 6-11 MC92600 Package Option Thermal Resistance Values .............................................. 7-8 Signal to Ball Mapping for 196 MAPBGA and 217 PBGA Packages ....................... 7-8 Components of a Character Name ..............................................................................B-2 Valid Data Characters..................................................................................................B-4 Valid Special Characters .............................................................................................B-8
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Tables
ix
Tables
Table Number Title Page Number
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About This Book
The primary objective of this reference manual is to describe the functionality of the MC92600 for software and hardware developers. Information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation, it is the readers' responsibility to be sure they are using the most recent version of the documentation.
Audience
It is assumed that the reader has the appropriate general knowledge regarding the design and layout requirements for high speed (Gbps) digital signaling and understanding of the basic principles of Ethernet and Fibre Channel communications protocols to use the information in this manual.
Organization
Following is a summary and a brief description of the major sections of this manual: * * * * Chapter 1, "Introduction," gives an overview of the device features and shows a block diagram of the major functional blocks of the part. Chapter 2, "Transmitter," describes the MC92600 transmitter, its interfaces and operational options. Chapter 3, "Receiver," gives a description of the receiver. Chapter 4, "System Design Considerations," describes the system considerations for the MC92600, including clock configuration, device startup and initialization, and proper use of the configuration control signals. Chapter 5, "Test Features," covers the system accessible test modes. Chapter 6, "Electrical Specifications and Characteristics," describes the DC and AC electrical characteristics. Chapter 7, "Package Description," provides the package parameters and mechanical dimensions and signal pin to ball mapping tables for the MC92600 device. Appendix A, "Ordering Information," provides the Motorola part numbering nomenclature for the MC92600 transceiver.
* * * *
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About This Book
xi
* *
Appendix B, "8B/10B Coding Scheme," provides tables of the fibre channel-specific 8B/10B encoding and decoding is based on the ANSI FC-1 fibre channel standard. "Glossary of Terms and Abbreviations" contains an alphabetical list of terms, phrases, and abbreviations used in this book.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as general information about the architecture.
General Information
The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street, Sixth Floor, San Francisco, CA, provides useful information about the PowerPC architecture and computer architecture in general: * The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, by International Business Machines, Inc. For updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html. Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David A. Patterson Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A. Patterson and John L. Hennessy
* *
Related Documentation
Motorola documentation is available from the sources listed on the back cover of this manual; the document order numbers are included in parentheses for ease in ordering: * Reference manuals--These books provide details about individual device implementations. The MC92600 QUAD SERDES Evaluation Kit Manual (MC92600EVK/D) describes how to use the design verification board and should be read in conjunction with this manual, the MC92600 Quad 1.25 Gbaud SERDES User's Manual (MC92600UM/D). Addenda/errata to reference manuals--Because some devices have follow-on parts an addendum is provided that describes the additional features and functionality changes. These addenda are intended for use with the corresponding reference's manuals. Hardware specifications--Hardware specifications provide specific data regarding bus timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations. This manual contains all the hardware specifications for the MC92600.
*
*
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* *
*
Application notes--These short documents address specific design issues useful to programmers and engineers working with Motorola processors. White Paper-These documents provide detail on a specific design platform and are useful to programmers and engineers working on a specific product. MC92610 3.125 Gbaud Reference Design Platform (BR1570/D) describes the technical design process used in developing a high-speed backplane reference design. Additional literature is published as new processors become available. For a current list of documentation, refer to http://www.motorola.com/semiconductors.
Conventions
This document uses the following notational conventions: Book titles in text are set in italics Internal signals are set in italics, for example, loop_back_data 0x 0b x x n Prefix to denote hexadecimal number Prefix to denote binary number In some contexts, such as signal encodings, an un-italicized x indicates a don't care. An italicized x indicates an alphanumeric variable. An italicized n indicates an numeric variable.
Signals
A bar over a signal name indicate that the signal is active low--for example, XMIT_A_IDLE and XMIT_B_IDLE. Active low signals are referred to as asserted (active) when they are low and negated when they are high. Signals that are not active low, such as XMIT_EQ_EN and DROP_SYNC are referred to as asserted when they are high and negated when they are low.
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About This Book
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Chapter 1 Introduction
The purpose of this user's manual is to explain the functionality of the MC92600 Quad 1.25 Gbaud SERDES transceiver and enables its use by software and hardware developers. The audience for this publication, therefore, consists of hardware designers and application programmers who are building data path switches and high-speed backplane intercommunication applications.
1.1
Overview
The MC92600 is a high-speed, full-duplex, serial data interface that can be used to transmit or receive data between chips across a board, through a backplane, or through cabling. The MC92600 has four transceivers each transmits and receives coded data at a rate of 1.0 gigabit per second (Gbps) through each of the four 1.25 gigabaud links. The MC92600's rich feature set makes it easily adaptable to many applications. The MC92600 is carefully designed for low-power consumption. Its 0.25 micron CMOS implementation nominally consumes 780mW with all links operating at full speed.
1.2
* * * * * * *
Features
Four full-duplex differential data links. Each transceiver can operate at 1.25 Gbaud or 0.625 Gbaud. Low power, approximately 800mW under typical conditions, while operating all transceivers at full speed. Internal 8B/10B encoder/decoder is accessed through the byte interface or is bypassed in 10-bit interface mode. Single and double data rate interfaces. Received data may be aligned to the recovered clock or to the reference clock. Drives 50 or 75 ohm media (100 or 150 ohm differential) for lengths of up to 1.5 meters board/backplane, or 10 meters of coax.
The following are the features of the MC92600:
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Chapter 1. Introduction
1-1
Block Diagram
* * * * * * * *
Link-to-link synchronization supports aligned word transfers. Tolerates +40 bit-times of link-to-link media delay skew. Selectable transmitter/receiver byte alignment modes enable unaligned transfers or aligned transfers with automatic realignment. Repeater mode configures the MC92600 into a 4-link receive-transmit repeater. Tolerates frequency offset in excess of +250ppm. On-chip receiver link termination. Receiver link inputs "hot swap" compatible. On-chip 50 ohm series source termination of TTL parallel outputs. Built-in self test for production test and on-board diagnostics.
1.3
Block Diagram
The MC92600 is a highly integrated device containing all of the logic needed to facilitate the application and test of a high-speed serial interface. No external components, other than the normal power supply decoupling network are required. A block diagram of the MC92600 device is shown in Figure 1-1.
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Block Diagram
XMIT_A_[7:0] XMIT_A_K XMIT_A_IDLE BIST RECV_A_[7:0] RECV_A_K RECV_A_9 RECV_A_IDLE RECV_A_ERR RECV_A_RCLK
Transmitter
8B/10B Encoder
XLINK_A_N XLINK_A_P
Align FIFO
8B/10B Decoder
RLINK_A_P RLINK_A_N
Receiver
XMIT_B_[7:0] XMIT_B_K XMIT_B_IDLE BIST RECV_B_[7:0] RECV_B_K RECV_B_9 RECV_B_IDLE RECV_B_ERR RECV_B_RCLK HSE, DDRE, ADIE WSE, WSE_GEN RESET, STNDBY BSYNC_0, BSYNC_1 RCCE, TBIE, REPE TST_0, TST_1 LBE, LBOE REF_CLK
Transmitter
8B/10B Encoder
XLINK_B_N XLINK_B_P
Align FIFO
8B/10B Decoder
RLINK_B_P RLINK_B_N
Receiver
LINK CONTROLLER PLL
MEDIA
Transmitter
XMIT_C_[7:0] XMIT_C_K XMIT_C_IDLE RECV_C_[7:0] RECV_C_K RECV_C_9 RECV_C_IDLE RECV_C_ERR RECV_C_RCLK
BIST
8B/10B Encoder
XLINK_C_N XLINK_C_P
Align FIFO
8B/10B Decoder
RLINK_C_P RLINK_C_N
Receiver
XMIT_D_[7:0] XMIT_D_K XMIT_D_IDLE RECV_D_[7:0] RECV_D_K RECV_D_9 RECV_D_IDLE RECV_D_ERR RECV_D_RCLK BIST
Transmitter
8B/10B Encoder
XLINK_D_N XLINK_D_P
Align FIFO
8B/10B Decoder
RLINK_D_P RLINK_D_N
Figure 1-1. MC92600 Block Diagram
Receiver
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Chapter 1. Introduction
1-3
References
1.4
References
[1] Fibre Channel, Gigabit Communications and I/O for Computer Networks, Benner, 1996. [2] Byte Oriented DC Balanced 8B/10B Partitioned Block Transmission Code, U.S. Patent #4,486,739, Dec. 4, 1984.
This section contains the indexed references in the document.
1.5
Revision History
Table 1-1. Revision History Table
Table 1-1 contains a brief description of the technical updates made to this document.
Document Revision Rev 1 Rev 2
Substantive Changes First release of the MC92600 User's Manual Second release of the MC92600 User's Manual with minor edits.
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Chapter 2 Transmitter
This chapter describes the MC92600 transmitter, and has five sections: * * * * * Section 2.1, "Transmitter Block Diagram" Section 2.2, "Transmitter Interface Signals" Section 2.3, "Transmission Modes" Section 2.4, "Types of Transmission Data" Section 2.5, "Device Operations"
The transmitter takes the data byte presented at its data input, creates a transmission character using its 8B/10B encoder (if not in 10-bit interface mode), and serially transmits the character out of the differential link output pads. A detailed explanation of the 8B/10B coding scheme is offered in Appendix B, "8B/10B Coding Scheme."
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Chapter 2. Transmitter
2-1
Transmitter Block Diagram
2.1
Transmitter Block Diagram
MEDIA Serialization Register DDRE TBIE REPE TST_0 TST_1 LBE LBOE Input Register Input Register (loop_back_en) (xmit_en) XLINK_x_P XMIT Driver XLINK_x_N
A block diagram of the MC92600 transmitter is shown in Figure 2-1.
8B/10B Encoder XMIT Controller
rx_clock
loop_back_data
WSE_GEN REF_CLK XMIT_x_[7:0] XMIT_x_K XMIT_x_IDLE repeat_data BIST Sequence Generator
Figure 2-1. MC92600 Transmitter Block Diagram
2.2
Transmitter Interface Signals
This section describes the interface signals of the MC92600 transmitters. Each signal is described, including its name, description, function, direction, and active state in Table 2-1. The table's signal names use the letter "x" as a place holder for links "A" through "D". Internal signals are not available at the I/O of the device, but are presented to illustrate device operation.
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Transmitter Interface Signals
Table 2-1. MC92600 Transmitter Interface Signals
Signal Name XMIT_x_7 through XMIT_x_0 XMIT_x_K Description Transmit byte Function Uncoded data/control byte to transmit. The least significant 8 bits of coded data to transmit in TBI mode. Indicates that transmit byte is a special control byte. Must be decoded with XMIT_x_IDLE and WSE_GEN to determine action, see Table 2-2. Coded transmit data bit 8 in TBI mode. This signal also affects receiver operation. See Section 3.2. Transmit an idle character. Must be decoded with XMIT_x_K and WSE_GEN to determine action, see Table 2-2. Coded transmit data bit 9 in TBI mode. Transmit a disparity-style word synchronization event. Must be decoded with XMIT_x_IDLE and XMIT_x_K to determine action, see Table 2-2. This signal also affects receiver operation. See Section 3.2. Activate digital loopback path, such that data transmitted is looped back to its receiver. Indicates that link outputs remains active when LBE is asserted. When LBOE is low, link outputs are disabled when LBE is asserted. Indicates that coded 10-bit data is at inputs and to bypass internal 8B/10B coding. When enabled, the transmitter obtains transmit data from the receiver. When enabled, link is operated at half-speed. Both data and link interfaces run at half speed. Direction Input Active State --
Special data indicator
Input
High
XMIT_x_IDLE
Transmit idle character bar
Input
Low
WSE_GEN
Word synchronization event generate
Input
High
LBE
Loop back enable
Input
High
LBOE
Loop back output enable
Input
High
TBIE
10-bit interface enable
Input
High
REPE HSE
Repeater mode enable Half speed enable
Input Input
High High
DDRE
Double data rate enable Indicates that the data interfaces are running at double data rate (data is sampled on the rising and falling edges of reference clock). Reference clock System reference clock to which the transmit interfaces are timed. Frequency requirement is dependent on HSE and DDRE settings. See Section 3.6 and Table 3.6 for configuration options.
Input
High
REF_CLK
Input
--
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Chapter 2. Transmitter
2-3
Transmission Modes
Table 2-1. MC92600 Transmitter Interface Signals (continued)
Signal Name MEDIA Description Function Direction Input Active State --
Media impedance select Indicates the impedance of the transmission media. Low indicates 50 and high indicates 75. Link serial transmit data Differential serial transmit data output pads.
XLINK_x_N/ XLINK_x_P Internal Signals rx_clock repeat_data loop_back_data
Output
--
High speed transceiver clock Received repeat data Loop back data
Internal, differential high-speed clock used to transmit and receive link data. Repeater mode, received data to retransmit. Differential loop back transmit data.
Input Input Output
-- -- --
2.3
2.3.1
Transmission Modes
Double Data Rate Mode
MC92600 accepts two transmission modes: double data rate mode and repeater mode.
Double data rate (DDR) mode enables sampling and storage of the data inputs to the transmitter on the rising and falling edges of REF_CLK. Data is placed in the transmit data input register. DDR mode is used to lower reference clock frequency while maintaining throughput, reducing board design complications. Table 4-1, "Legal Reference Clock Frequency Ranges" shows legal reference clock frequencies for all modes of operation. DDR mode is enabled by asserting DDRE.
2.3.2
Repeater Mode
Repeater mode configures the MC92600 into a 4-link receive-transmit repeater so that data can enter serially and exit serially. In this mode, the data to transmit is obtained from its receiver (transmitter A gets receiver A's data, transmitter B gets receiver B's data, and so on). The transmit input signals, XMIT_x_7 through XMIT_x_0, XMIT_x_K, and XMIT_x_IDLE are ignored. Repeater mode is enabled by setting REPE high. In repeater mode transmit data is sampled and stored in the transmit data input register on the rising edge of the reference clock (REF_CLK). See Section 3.5.4.5, "Repeater Mode" for more information on repeater mode. NOTE When using repeater mode ground all parallel inputs because input I/Os do not have internal pulldowns.
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Types of Transmission Data
2.4
2.4.1
Types of Transmission Data
Transmitting Uncoded Data
The MC92600 can handle both coded and uncoded data.
Uncoded data is presented in 8-bit bytes to the transmit data input register through the XMIT_x_7 through XMIT_x_0 signals. The uncoded data is coded into 10-bit transmission characters using an on-chip 8B/10B encoder. The 8B/10B coding ensures DC balance across the link and sufficient transition density to facilitate reliable data recovery. The XMIT_x_7 through XMIT_x_0 signals are interpreted as data when the XMIT_x_K signal is low. The 8B/10B code includes special control codes. Special control codes may be transmitted by setting the XMIT_x_K high, XMIT_x_IDLE high, and WSE_GEN low as indicated in Table 2-2. The transmit byte is assumed to be a control code in this state. The transmitter generates an idle character (K28.5) when XMIT_x_K is high, XMIT_x_IDLE is low, and WSE_GEN is low as indicated in Table 2-2. An idle character of proper running disparity is generated when this state is asserted; the state on the XMIT_x_7 through XMIT_x_0 signals is ignored. This eases generation of idle characters needed for byte and word synchronization and allows the link to maintain alignment when transmission of data is not needed. When using the device in a system where word alignment is required (see Section 3.5.2, "8B/10B Decoder Operation"), it may be desirable to generate disparity-style word synchronization events. This is especially important where compatibility with older transceivers is required. A disparity style word synchronization event is generated by setting WSE_GEN high and XMIT_x_K high for each transmitter for which word synchronization event generation is desired. The transmitter generates one of two unique 16-character idle (K28.5) sequences depending on the current running disparity:
I+, I+, I-, I-, I+, I-, I+, I-, I+, I-, I+, I-, I+, I-, I+, Ior I-, I-, I+, I+, I-, I+, I-, I+, I-, I+, I-, I+, I-, I+, I-, I+
where I+ stands for idle of positive disparity, and I- stands for idle of negative disparity.
Table 2-2. Transmitter Control States
WSE_GEN Low High XMIT_x_IDLE Don't care Don't care XMIT_x_K Low Low (on all four transmitters) High Description Transmit data present on XMIT_x_7-0 inputs. Transmit data present on XMIT_x_7-0 inputs and force invalidation of receivers' current byte and word alignment. Transmit idle (K28.5), ignore XMIT_x_7-0 inputs.
Low
Low
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Table 2-2. Transmitter Control States
WSE_GEN Low High XMIT_x_IDLE High don't care XMIT_x_K High High Description Transmit control present on XMIT_x_7-0 inputs. Transmit disparity-style word synchronization event, ignore XMIT_x_7-0 inputs.
The transmitter inputs, XMIT_x_7-XMIT_x_0, XMIT_x_K and XMIT_x_IDLE are ignored for the next 15 byte-times while the sequence is transmitted. NOTE The transmitter control signals WSE_GEN and XMIT_x_K also affect the receiver. When WSE_GEN is high and XMIT_x_K is low on all four links, the receiver invalidates its current byte alignment and word synchronization. See Section 3.3.2.1, "Word Synchronization Method" for more information on this function.
2.4.2
Transmitting Coded Data
10-bit coded data may be transmitted, bypassing the internal 8B/10B encoder. 10-bit interface (TBI) mode is enabled by asserting TBIE. In this mode, the ten bits of data to transmit are presented on the XMIT_x_7-XMIT_x_0 inputs, and bits 8 and 9 on the XMIT_x_K and XMIT_x_IDLE inputs, respectively. Special care must be taken when using TBI mode. The 10-bit data must exhibit the same properties as 8B/10B coded data. DC balance must be maintained and there must be sufficient transition density to ensure reliable data recovery at the receiver. The receiver requires that the K28.5 idle character be periodically transmitted to enable byte and word synchronization. This 10-bit pattern (`0011111010' or `1100000101', ordered from bit 0 through 9) is used for alignment and link-to-link synchronization when operating in any of the byte or word synchronization modes. The pattern of idles and data required to achieve byte or word synchronization depends on the configuration of the receiver, see Section 3.3.1, "Byte Alignment." The appropriate sequence must be applied through the 10-bit interface. The automated facilities to generate idles and word-synchronization events are disabled in TBI mode. The WSE_GEN input does not cause the generation of word synchronization events in TBI mode. However, WSE_GEN does work in conjunction with XMIT_x_K to invalidate receiver byte alignment and word synchronization as described in the previous section.
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Device Operations
2.5
Device Operations
The MC92600 transmitter is comprised of several components whose operations are described in the following sections.
2.5.1
8B/10B Encoder Operation
The 8B/10B encoder transforms 8-bit data/control characters from the input register into 10-bit transmission characters. The fibre channel 8B/10B coding standard is followed [1,2]. Running disparity is maintained and the appropriate transmission characters are produced, maintaining DC balance and sufficient transition density to allow reliable data recovery at the receiver. See Appendix B, "8B/10B Coding Scheme" for a detailed description of 8B/10B coding. The inputs to the 8B/10B encoder are the data byte (XMIT_x_7 through XMIT_x_0), special code signal (XMIT_x_K) and transmit idle signal (XMIT_x_IDLE). Data and legal control bytes are coded according to the 8B/10B method. Illegal control bytes produce unpredictable transmission characters, leading to disparity and coding errors, ultimately reducing link reliability. The 8B/10B encoder produces an idle character of proper running disparity when XMIT_x_IDLE is low, XMIT_x_K is high, and WSE_GEN is low, as indicated in Table 2-2, "Transmitter Control States." The 8B/10B encoder is bypassed in TBI mode.
2.5.2
Transmit Driver Operation
The transmit driver drives transmission characters serially across the link. Two bits per transceiver clock, one each on the rising and falling transceiver clock (rx_clock) edges, are transmitted differentially from the XLINK_x_P (positive) and XLINK_x_N (negative) outputs. The rx_clock runs at 625 MHz for 1 Gbps (1.25 gigabaud) operation and at 312.5 MHz for 500 Mbps (625 megabaud) operation. The transmit driver is a controlled impedance driver. The impedance of the driver is programmable to 50 or 75 through the MEDIA signal. Drive impedance is 50 when MEDIA is low and 75 when MEDIA is high. A special loop-back mode is supported for test. Asserting the LBE signal high enables loop-back mode causing the state being driven on XLINK_x_P/XLINK_x_N to be looped back to the input amplifier of the link's receiver. Loop-back data is processed the same as normally received data. Loop-back enables at-speed self-test to be implemented for production test and for in-system self-test. The loop-back signals are electrically isolated from the XLINK_x_P/XLINK_x_N output signals. Therefore, if the outputs are shorted, or otherwise restricted, the loop-back signals still operate normally. When in loop-back mode, the LBOE signal controls the action of the XLINK_x_P/XLINK_x_N output signals. When
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Device Operations
LBOE is low, the transmit driver holds the XLINK_x_P/XLINK_x_N output signals high and low, respectively. When LBOE is high, the XLINK_x_P/XLINK_x_N output signals continue to operate normally. See Chapter 5, "Test Features" for more information on test modes. NOTE For normal transmitter operation (TST_0, TST_1 and LBE all low) LBOE must also be low or the receivers will not function. See Section 5.7, "Board Level Manufacturing Test Mode" for more information. The electrical specifications of the transmitter's driver are found in Table 6-3, "DC Electrical Specifications for 3.3V Power Supply" or in Table 6-4, "DC Electrical Specifications for 2.5V Power Supply."
2.5.3
Transmit Data Input Register Operation
The transmit data input register accepts data to be transmitted and synchronizes it to the internal clock domain. Transmit data is normally uncoded 8-bit data, however, transmission of coded 10-bit data is supported in 10-bit interface (TBI) mode. TBI mode is enabled by asserting TBIE high. Transmit data is sampled and stored in the input register on the rising edge of the reference clock (REF_CLK). The transmitter supports double data rate (DDR) mode where data is sampled and stored on both the rising and falling edges of REF_CLK. DDR mode is enabled by asserting DDRE high.
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Chapter 3 Receiver
This section describes the MC92600 receiver, its interfaces, and operation. This chapter has the following sections: * * * * * * * Section 3.1, "Receiver Block Diagram" Section 3.2, "Receiver Interface Signals" Section 3.3, "Alignment Modes" Section 3.4, "Receiver Clock Timing Modes" Section 3.5, "Device Operations" Section 3.6, "Receiver Interface Error Codes" Section 3.6, "Receiver Interface Error Codes"
The receiver is a dual-rate receiver, operating at 1 Gbps or 500 Mbps (1.25 or 0.625 Gbaud) rates. The receiver is based upon a 16X oversampled transition tracking loop data recovery method. A block diagram of the MC92600 receiver is found in Figure 3-1.
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Receiver Block Diagram
3.1
Receiver Block Diagram
loop_back_data
rx_clock
MEDIA RLINK_x_P
RECV Amp
RLINK_x_N HSE BSYNC_0 BSYNC_1
Delay Line, 16 Samples
Idle Detection & Byte Alignment
Transition Tracking Loop & Data Recovery
WSE_GEN XMIT_x_K
recv_byte_clock
8B/10B Decoder TBIE
idle_detect
WSE
Word Alignment drop/add
Alignment FIFO
TST_0 TST_1
REF_CLK RCCE DDRE ADIE
Timing Alignment
BIST/BERT Analyzer
repeat_data
over_underrun Receiver Interface
REPE
RECV_x_[7:0] RECV_x_K RECV_x_9 RECV_x_IDLE RECV_x_ERR RECV_x_RCLK
Figure 3-1. Receiver Block Diagram
3.2
Receiver Interface Signals
This section describes the interface signals of the MC92600 receiver. Each signal is described, including its name, function, direction and active state in Table 3-1. The table's signal names use the letter "x" as a place holder for links "A" through "D". Internal signals are not available at the I/O of the device, but are presented to illustrate device operation.
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Receiver Interface Signals
Table 3-1. MC92600 Receiver Interface Signals
Signal Name RECV_x_7 through RECV_x_0 Description Function Direction Output Active State --
Received byte (bits 7-0) Received and decoded data/control byte. The least significant 8 bits of received coded data in TBI mode. Special data indicator/ Received bit 8 Indicates that received byte is a special control byte. Received coded bit 8 in TBI mode. Errors are coded using this signal. See Section 3.6 for error codes. Received coded bit 9 in TBI mode. Unused in 8-bit mode. Indicates that the receiver detected an idle character (operates in Byte and TBI modes). Errors are coded using this signal. See Section 3.6 for error codes. Indicates that the receiver detected an error. RECV_x_IDLE and RECV_x_K must be decoded to determine error condition. See Section 3.6 for error codes. Internally generated clock used for reading receiver outputs when RCCE is asserted. This signal when asserted coincident with XMIT_x_K set low on all four links invalidates current byte alignment and word synchronization. This signal also affects transmitter operation. See Section 2.2. This signal when set low on all four links coincident with WSE_GEN asserted invalidates current byte alignment and word synchronization. This signal also affects transmitter operation. See Section 2.2. Indicates that the receiver interface is in 10-bit mode and that the 8B/10B decoder is bypassed. Indicates to operate link at half-speed. Both data and link interfaces run at half speed. Indicates that all four receivers are being used in unison to receive synchronized data.
RECV_x_K
Output
--
RECV_x_9 RECV_x_IDLE
Received bit 9 Receiver idle detect
Output Output
-- --
RECV_x_ERR
Receiver error
Output
--
RECV_x_RCLK
Receiver recovered Byte clock Word synchronization Event generate
Output
--
WSE_GEN
Input
--
XMIT_x_K
Special data indicator
Input
--
TBIE
10-bit interface enable
Input
High
HSE
half-speed enable
Input
High
WSE
Word synchronization enable
Input
High
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Alignment Modes
Table 3-1. MC92600 Receiver Interface Signals (continued)
Signal Name DDRE Description Double data rate enable Function Indicates that the data interfaces are running at double data rate (data is output on the rising and falling edges of clock.) Establishes DDR mode. Defines the of word synchronization event method. See Section 3.3.2. Indicates the type of byte alignment to employ in the receiver. See Section 3.3.1. Direction Input Active State High
BSYNC_0 BSYNC_1
Byte alignment mode Byte alignment mode
Input Input
High --
RCCE
Recovered clock enable Indicates that the output data is synchronized to its recovered byte clock. Otherwise output data is synchronized to the reference clock. Add/delete idle enable Indicates that the receiver is free to add/delete idle characters to/from the output data stream to maintain alignment. When enabled, the transmitter obtains transmit data from the receiver. Indicates operating/test mode of the chip. See Chapter 5. System reference clock to which the receiver interfaces may be timed. Provided frequency is dependent on HSE and DDRE settings. Differential serial receive data input pads.
Input
High
ADIE
Input
High
REPE TST_0/ TST_1 REF_CLK
Repeater mode enable Test mode Reference clock
Input Input Input
High -- --
RLINK_x_N/ RLINK_x_P Internal Signals rx_clock loop_back_data repeat_data
Link serial receive data
Input
--
High speed transceiver clock Loop back data Received repeat data
Internal, differential high speed clock used to transmit and receive link data. Differential loop back receive data. Repeater mode, received data to re-transmit.
Input Input Output
-- -- --
3.3
Alignment Modes
The MC92600 supports two types of alignment, byte alignment and word alignment. Byte alignment deals with the MC92600 being configured as four separate receivers. Word alignment deals with four receivers being configured to work together.
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Alignment Modes
3.3.1
Byte Alignment
The receiver supports three modes of byte alignment as defined by the BSYNC_0, BSYNC_1 and WSE signals. As described in Table 3-2, the three types of byte alignment modes: byte alignment with realignment, byte alignment with idle realignment and disparity-based word alignment, and non-aligned data.
Table 3-2. Byte Alignment Modes
Byte Alignment Mode Byte aligned with realignment Byte aligned with idle realignment and disparity word alignment, see Section 3.3.2.1. Non-aligned BSYNC_0 High High High BSYNC_1 Low Low High WSE Low High Low
NOTE In byte alignment modes and not word synchronization (WSE = low), BSYNC_0 must be high.
3.3.1.1
Byte-Aligned with Realignment
At power-up, the receiver starts an alignment procedure, searching for the 10-bit pattern defined by the 8B/10B idle code. Synchronization logic checks for the distinct idle sequence, `0011111010' and `1100000101' (ordered bit 0 to bit 9), characteristic of the K28.5 idle pattern. The search is done on the 10-bit data in the receiver, and is therefore independent of TBI mode. Alignment requires a minimum of four, error-free, received idle characters to ensure proper alignment and lock. Non-idle characters may be interspersed with the idle characters. The disparity of the idle characters is not important to alignment and can be positive, negative or any combination. The receiver begins to forward received characters once locked on an alignment. However, if word synchronization is enabled (WSE = high), received characters are not forwarded to the receiver interface until the first, valid, non-idle character is received. Alignment remains locked until one of three events occurs that indicate loss of alignment: * Alignment is lost when a misaligned idle sequence is detected. A misaligned idle sequence is defined as four idle characters with an alignment different from the current alignment. Non-idle characters may be dispersed between the four misaligned idles, however, a properly aligned idle character breaks the sequence. Alignment is changed to the newly detected alignment without interrupting data flow through the receiver if in Byte Aligned Mode (WSE = low). However, if in Word Aligned Mode (WSE = high) word alignment is lost. Alignment is also lost when the number of received characters with 8B/10B coding errors outnumbers the non-error characters by four. Misalignment detection of this
*
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Alignment Modes
*
type is not available in TBI mode. The receiver restarts its alignment procedure and halts data flow until alignment is achieved. Finally, the user may force loss of alignment by asserting WSE_GEN high and XMIT_x_K low on all four receivers simultaneously. The receiver restarts its alignment procedure and halts data flow until alignment is achieved.
When establishing byte alignment, or when data flow is halted due to misalignment, the receiver's RECV_x_ERR signal is asserted high and the "Not Byte Sync" error is reported as described in Section 3.6, "Receiver Interface Error Codes."
3.3.1.2
Byte-Aligned with Idle Realignment and Disparity Word Alignment
This alignment mode is the same as the one described in Section 3.3.1.1, "Byte-Aligned with Realignment." The difference in this alignment mode is related to the style of word synchronization. Word synchronization between receivers is accomplished by synchronizing the received characters to a unique word synchronization event in the incoming character stream. In this byte alignment mode, the word synchronization event is defined to be a disparity-based idle sequence as described in Section 2.4.1, "Transmitting Uncoded Data." See Section 3.3.2.1, "Word Synchronization Method," for more information on word synchronization.
3.3.1.3
Non-Aligned
In this mode no attempt is made to align the incoming data stream. The bits are simply accumulated into 10-bit characters and forwarded. This mode should be used only with 10-bit interface mode (TBIE = high) and with word synchronization disabled (WSE = low).
3.3.2
Word Alignment
The four receivers in the MC92600 can be used cooperatively to receive 32-bit aligned word transfers. Word alignment is enabled by setting the word synchronization enable input, WSE, high. Word alignment, or word synchronization, is possible in both byte interface mode or in TBI mode. However, word synchronization is dependent on the detection of simultaneously transmitted word synchronization events that contain idle characters. Therefore, if operating in TBI mode, the idle character must be a supported member of the code set.
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Alignment Modes
3.3.2.1
Word Synchronization Method
Word synchronization aligns characters in the receiver's alignment FIFO. Synchronization is accomplished by lining up word synchronization events detected by each of the receivers, such that all are coincident at the same stage of their FIFO. A word synchronization event is defined differently depending on the state of the BSYNC_0 and BSYNC_1 signals. Table 3-3 shows the type of word synchronization event used.
Table 3-3. Word Synchronization Events
Word Synchronization Event 4 idle/1 non-idle Disparity-based idle sequence BSYNC_0 Low High BSYNC_1 don't care Low
There are two types of word synchronization events: the 4/1 idle sequence and the disparity-based idle sequence. * * The 4/1 idle sequence is defined as four consecutive idle characters followed by a non-idle character. The disparity-based idle sequence is 16 consecutive idle characters with improper disparity on the second and fourth idle character in the sequence. The disparity-based idle sequence is described further in Section 2.4.1, "Transmitting Uncoded Data."
Word synchronization events must be generated at all concerned transmitters simultaneously in order for synchronization to be achieved. Word synchronization events must be received at all concerned receivers within 40 bit-times of each other. Word synchronization events are used to establish a relationship between the received bytes in each of the receivers. The bytes of a word are matched and presented simultaneously at the receiver interface. Once synchronization is achieved, the receiver tolerates +/- 6 bit-times of drift between receivers. If drift exceeds +/- 6 bit-times, the receiver will continue to operate. However, the received bytes will no longer be synchronized properly because the receiver remains locked onto the initially established synchronization. Word synchronization remains locked until one of three events occurs that indicate loss of synchronization. Word synchronization lock can be lost in three ways: * * When one or more of the receivers lose or change byte alignment. Byte alignment loss is described in Section 3.3.1.1, "Byte-Aligned with Realignment." When overrun/underrun is detected on one or more of the receivers but not on all simultaneously, see Section 3.4.2, "Reference Clock Timing Mode" for more about overrun/underrun.
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Receiver Clock Timing Modes
*
When explicitly invalidated by asserting WSE_GEN high and XMIT_x_K low on all four receivers.
When lock is lost, word synchronization must be re-established before data flow through the receiver resumes. The receiver interface is disabled during initial word alignment. No data is produced at its outputs until word alignment is achieved and the first non-idle character is received. When establishing word alignment, or when word alignment is lost, the receiver's RECV_x_ERR signal is asserted high and the "Not Word Sync" error is reported as described in Section 3.6, "Receiver Interface Error Codes."
3.3.2.2
Word Synchronization Recommended Settings
Word alignment can only be used with certain operating modes and has limited application in others. Table 3-4 describes the relationship between modes and word synchronization.
Table 3-4. Word Synchronization Settings
Mode Word synchronization Byte synchronization Signals WSE BSYNC_0, BSYNC_1 ADIE Recommended State High Description Enables word synchronization.
Any mode except Word synchronization depends upon idle character non-aligned detection. Byte alignment is required for idle detection. High When enabled, allows the receiver to add/delete idle patterns to maintain word alignment. This is the recommended operating mode when the reference clock is being used to time the receiver interface (RCCE = Low) and there is a frequency offset between the transmitter and receiver. Idles are added or dropped to maintain word alignment. When enabled, the idle character must be part of the TBI code set. When disabled, the idle is naturally supported by the 8B/10B codes. Does not affect word synchronization. Does not affect word synchronization. Does not affect word synchronization.
Add/delete idle
10-bit interface
TBIE
don't care
Recovered clock Half-speed enable Double data rate
RCCE HSE DDRE
don't care don't care don't care
3.4
Receiver Clock Timing Modes
The receiver interface is timed to the recovered clock or to the reference clock depending on the state of the recovered clock enable, RCCE, signal. RCCE asserted enables timing relative to the recovered clock, and set low enables timing relative to the reference clock.
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Receiver Clock Timing Modes
3.4.1
Recovered Clock Timing Mode
The recovered clock signal, RECV_x_RCLK, is generated by the receiver and, on average, runs at the reference clock frequency of the transmitter at the other end of the link. The recovered clock is not generated by a clock recovery PLL, but is generated by the receiver bit-accumulation and byte-alignment logic. The RECV_x_RCLK signal is asserted high, generating a rising edge, whenever a new byte (character) is accumulated and available. To track a transmitter frequency that is offset from the receiver's reference clock frequency, the duty cycle and period of the recovered clock is modulated. The MC92600 is designed to tolerate up to +250 ppm of frequency offset. For example: if the transmitter is running 100 ppm faster than the receiver, then a short cycle is generated approximately every 2,000 received bytes. The short cycle has a period equal to eight bit-times instead of the normal ten bit-times. This implies that logic using received data timed to the recovered clock must be able to operate with a period equal to eight bit-times (6.4 ns for 1.25 gigabaud). Each short cycle recovers two bit-times of offset. Generally, the number of received bytes (characters) between short cycles is equal to: (2 * 106) / (10 * N) bytes where: N is the frequency offset in ppm. Alternately, if the transmitter is running 100 ppm slower than the receiver, then a long cycle is generated approximately every 2,000 received bytes. The long cycle has a period equal to twelve bit-times instead of ten bit-times. The above equation is also used to compute the period between long cycles. Data is timed to the rising edge of the recovered clock signal except in double data rate mode where data is timed to the rising and falling edges of the recovered clock. If the receivers are being operated in word synchronization mode (WSE = high), the data for all four receivers are timed relative to link A's recovered clock RECV_A_RCLK. NOTE Recovered clocks RECV_B_RCLK, RECV_C_RCLK, and RECV_D_RCLK are not aligned to the data in word synchronization mode and should not be used.
3.4.2
Reference Clock Timing Mode
Data is timed relative to the reference clock when RCCE is low. Synchronization between the recovered clock and the reference clock is handled by the receiver interface. Frequency offset between the transmitter's reference clock and the receiver's reference clock causes overrun/underrun situations. Overrun occurs when the transmitter is running faster than the receiver. Underrun occurs when the transmitter is running slower than the receiver.
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Device Operations
In an overrun situation, a byte of data needs to be dropped to maintain synchronization between the clock domains. The receiver interface searches for an idle byte to drop when overrun is imminent. However, the idle is dropped only if add/delete idle (ADI) mode is enabled by setting ADIE high. When enabled, idle patterns are dropped to maintain synchronization. If sufficient idle patterns are not available to drop, receiver overrun may occur. When overrun occurs, the overrun/underrun error is reported as described in Section 3.6, "Receiver Interface Error Codes," for one byte clock period. Overrun error is also reported if ADI mode is disabled and overrun occurs, even if idles are available to drop. A sufficient number of idles must be transmitted to guard against overrun. The frequency of idles can be computed based upon the maximum frequency offset between transmitter and receiver in the system. The number of bytes (characters) that can be transmitted between idles is: (106 / N) - 1 bytes where: N is the frequency offset in ppm. In an underrun situation, a byte of data needs to be added to maintain synchronization between the clock domains. The receiver interface adds an idle byte when underrun is imminent. However, the idle is added only if add/delete idle (ADI) mode is enabled by asserting ADIE. If ADI mode is disabled and underrun occurs, the overrun/underrun error is reported as described in Section 3.6 for one byte clock period. Data is timed to the rising edge of the reference clock signal except in double data rate mode where data is timed to the rising and falling edges of the reference clock.
3.5
Device Operations
The MC92600 receiver is comprised of several devices and operations that are described in the following sections.
3.5.1
Receiver Input Amplifier
The input amplifier connects directly to the link input pads RLINK_x_P and RLINK_x_N. It is a differential amplifier with an integrated analog multiplexer for loop-back testing. Link termination resistors are integrated with the amplifier. The termination resistance is programmable to be 100 differential or 150 differential through the MEDIA signal. Termination resistance is 100 when MEDIA is low and 150 when MEDIA is high. The input amplifier facilitates a loop-back path for production and in-system testing. When the MC92600 is in loop-back mode (LBE is high), the input amplifier selects the loop-back differential input signals and ignores the state on the RLINK_x_P and RLINK_x_N signals.
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This allows in-system loop-back BIST independent of the current input state. See Chapter 5 for more information on test modes. The input amplifier's electrical specifications may be found in Table 6-3, "DC Electrical Specifications for 3.3V Power Supply" and in Table 6-4, "DC Electrical Specifications for 2.5V Power Supply."
3.5.2
8B/10B Decoder Operation
The 8B/10B decoder takes the 10-bit character from the transition tracking loop and decodes it according to the 8B/10B coding standard [1,2]. The decoder does two types of error checking. First it checks that all characters are a legal member of the 8B/10B coding space. The decoder also checks for running disparity errors. If the running disparity exceeds the limits set in the 8B/10B coding standard then a disparity error is generated. See Appendix B, "8B/10B Coding Scheme." An illegal character or disparity error sets the RECV_x_ERR signal high, coincident with the received data for a 1-byte output period. The "Code Error" or "Disparity Error" is reported as described in Section 3.6, "Receiver Interface Error Codes." It is difficult to determine the exact byte that caused the disparity error, so it should not be associated with a particular received byte. It is rather a general indicator of the improper operation of the link. Its intended use is for the system to monitor link reliability. The 8B/10B decoder is bypassed when operating in 10-bit interface mode (TBIE = high.)
3.5.3
Transition Tracking Loop and Data Recovery
The received differential data from the input amplifier is sent to the transition tracking loop for data recovery. The MC92600 uses an oversampled transition tracking loop method for data recovery. The differentially received data is sampled and processed digitally providing for low bit error rate (better than 10 -12) data recovery of a distorted bit stream. The transition tracking loop is tolerant of frequency offset between the transmitter and receiver. The MC92600 reliably operates with +250 ppm of frequency offset. The MC92600 is tolerant of frequency offset between the transmitter and receiver. The MC92600 reliably operates with +250 ppm of frequency offset. The device's transition tracking loop method is different than the typical PLL clock recovery method. Its receiver compensates for overrun and underrun caused by frequency offset by modulating the duty-cycle and period of the received byte clock. Recovered data is accumulated into 10-bit characters. Characters are aligned to their original 10-bit boundaries if a byte alignment mode is enabled.
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3.5.4
Receiver Interface Modes
The receiver interface facilitates transfer of received data to the system. It also provides information on the status of the link. Table 3-1, "MC92600 Receiver Interface Signals," describes each of the signals involved in receiver operation. The receiver interface, through which received data is obtained, may be operated in byte mode or in 10-bit interface mode. Several timing mode options exist for the receiver interface. Each of the operating modes are described in the following sections. * * * * * Section 3.5.4.1, "Byte Interface Mode" Section 3.5.4.2, "10-Bit Interface Mode" Section 3.5.4.3, "Double Data Rate Mode" Section 3.5.4.4, "Half-Speed Mode" Section 3.5.4.5, "Repeater Mode"
3.5.4.1
Byte Interface Mode
The receiver interface may be operated in byte mode or in 10-bit interface (TBI) mode. Received data is a byte (8 bits) of uncoded data when in byte mode. Byte interface mode is enabled by setting the TBIE signal low. NOTE Do not use non-aligned mode in byte interface mode. See Section 3.3.1, "Byte Alignment" for more information on byte alignment modes. The internal 8B/10B decoder is used to decode data from the 10-bit character received. The received byte is on the RECV_x_7 through RECV_x_0 signals. The RECV_x_K is asserted when the byte represents a special 8B/10B code, otherwise it is low, indicating that the byte is normal data. The RECV_x_IDLE is asserted when the byte is the special 8B/10B idle (K28.5) code. This can be used by system logic for synchronization or data parsing. RECV_x_IDLE is set low when the byte is normal data or a non-idle special code. RECV_x_IDLE is asserted and RECV_x_K is set low to indicate that an underrun/overrun error occurred. See Section 3.6, "Receiver Interface Error Codes" for more information on error conditions. The RECV_x_ERR is set low when the receiver is operating normally, and is asserted when received data contains an error or the receiver is in an error state. The state of the RECV_x_IDLE and RECV_x_K signals are decoded to determine the error condition. Table 3.6, "Receiver Interface Error Codes" describes the error codes and their meaning. The receiver interface is timed to the recovered clock, RECV_x_RCLK, or to the reference clock, REF_CLK, depending on the state of the RCCE signal.
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Device Operations
3.5.4.2
10-Bit Interface Mode
Received data is ten bits of coded data when in TBI mode. The internal 8B/10B decoder is not used, and it is assumed that decoding is done externally. 10-bit data is made up from the collection of signals-- RECV_x_9, RECV_x_K, and RECV_x_7 through RECV_x_0 making up bits 9 through 0, respectively. 10-bit interface mode is enabled by setting the TBIE signal high. The RECV_x_IDLE is asserted when the 10-bit character is the special 8B/10B idle (K28.5) code. This can be used by system logic for synchronization or data parsing. RECV_x_IDLE is set low when the data is normal data or a non-idle special code. The RECV_x_ERR is set low when the receiver is operating normally, and is asserted when the receiver is in an error state. The state of the RECV_x_IDLE signal is decoded to determine the error condition. Table 3-6 describes the error codes and their meaning. The receiver interface is timed to the recovered clock, RECV_x_RCLK, or to the reference clock, REF_CLK, depending on the state of the RCCE signal.
3.5.4.3
Double Data Rate Mode
Double data rate (DDR) mode, enabled when DDRE is asserted, allows the received data to be output on the rising and falling edges of a reference or recovered clock. DDR mode is used to lower reference clock frequency while maintaining throughput, reducing board design complications. It is important to note that in DDR mode the legal range of reference clock frequencies is reduced. Table 4-1, "Legal Reference Clock Frequency Ranges" shows legal reference clock frequencies for all modes of operation.
3.5.4.4
Half-Speed Mode
Half-speed (HS) mode, enabled when HSE is asserted, operates the receiver in its lower speed range. In HS mode, the link speed is 500 Mbps (625 Mbaud.) The receiver interface operates at half speed as well, in pace with received data.
3.5.4.5
Repeater Mode
Repeater mode configures the MC92600 into a 4-link receive-transmit repeater. In this mode, received data is forwarded to the transmitter for re-transmission. Link A's receiver forwards to link A's transmitter, link B's receiver to link B's transmitter, and so on. The receiver's data outputs and status signals reflect the received data and the current status of the receiver. See Section 2.3.2, "Repeater Mode" for more information on repeater mode.
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3-13
Receiver Interface Error Codes
3.6
Receiver Interface Error Codes
The receiver's status and data error conditions are coded on the RECV_x_ERR, RECV_x_IDLE and RECV_x_K signals. When RECV_x_ERR is low, the receiver is operating normally and no error conditions exist (with exception of underrun/overrun error in byte mode.) When RECV_x_ERR is high, the data on the receiver's output is questionable due to an error condition or lack of synchronization. Initially, RECV_x_ERR is asserted indicating that the receiver is in one of its start-up phases. Table 3-5 describes the error conditions and their signal coding for byte interface mode.
Table 3-5. Receiver Interface Error Codes (Byte Interface)
RECV_x_ERR Low Low RECV_x_K Low Low RECV_x_IDLE Low High Priority 8 3 Description Normal operation, valid data character received. Overrun/Underrun--The receiver interface synchronization logic detected an overrun/underrun condition. Data may be dropped or repeated. Normal operation, valid control character received. Normal operation, valid idle (K28.5) character received. Code Error--The 8B/10B decoder detected an illegal character. Disparity Error--The 8B/10B decoder detected a disparity error. Not byte Sync--The receiver is in start-up or has lost byte alignment and is searching for alignment. Not Word Sync--The receiver is byte synchronized but has not achieved or has lost word alignment and is searching for alignment.
Low Low High High High High
High High Low Low High High
Low High Low High Low High
7 6 4 5 1 2
Table 3-6 describes the error conditions and their signal coding for 10-bit interface mode.
Table 3-6. Receiver Interface Error Codes (10-Bit Interface)
RECV_x_ERR Low Low High High RECV_x_IDLE Low High Low High Priority 4 3 1 2 Description Normal operation, non-idle character received. Normal operation, idle (K28.5) character received. Not byte/word sync--The receiver is in start-up or has lost byte or word alignment and is searching for alignment. Overrun/Underrun--The receiver interface synchronization logic detected and overrun/underrun condition. Data may be dropped or repeated.
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Chapter 4 System Design Considerations
This chapter describes the system considerations of the MC92600 Quad DDR, including device-startup, initialization, and the proper use of the standby and repeater modes.
4.1
Reference Clock Configuration
Table 4-1. Legal Reference Clock Frequency Ranges
The legal ranges of reference clock frequencies vary depending on the operating modes selected. Table 4-1 shows the ranges allowed for each mode of operation.
Reference Frequency Min (MHz) 95.00 47.50 47.50 23.75 Reference Frequency Max (MHz) 135.0 67.50 67.50 33.75 Link Transfer Rate (Gigabaud) 1.350-0.950 0.675-0.475 1.350-0.950 0.675-0.475
DDRE Low Low High High
HSE Low High Low High
4.2
Start-up
The MC92600 begins a start-up sequence upon application of the reference clock (REF_CLK input) to the device. This is considered a cold start-up. The receiver requires that byte alignment is reached before data can be transmitted. If word synchronization is selected, then word alignment must occur. The steps in the cold start-up sequence are as follows: 1. 2. 3. 4. PLL start-up Receiver initialization and byte alignment Word alignment (if enabled) Run
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4-1
Start-up
The expected duration of each step in the start-up sequence is shown in Table 4-2. A cold start-up can be initiated at any time by asserting the RESET signal low. It is recommended that RESET be set low at initial start-up, however, it is not strictly required.
Table 4-2. Start-up Sequence Step Duration
Start-up Step PLL start-up Receiver initialization Typical Duration (in Bit Times)* 10240 + 25 s 50 160 Word alignment 50 160 WSE = low WSE = high WSE = low WSE = high Note
* Example: if the Reference Clock Frequency is 125 MHz, then the bit time equals 800 ps.
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Standby Mode
4.3
Standby Mode
Standby mode puts the MC92600 into a low power, inactive state. When STNDBY is asserted, the device will force all transmitter link outputs to their disabled state as defined in Section 2.5.2, "Transmit Driver Operation," and will disable all internal clocking. An important feature of standby mode is that the internal PLL is not disabled. It remains operating and locked to the reference clock. Keeping the internal PLL enabled greatly reduces the time needed to recover from standby mode to run mode, because only the receiver initialization and word alignment start-up steps are required.
4.4
Repeater Mode
To send 32 bytes of data the MC92600 can be configured into a four-link receive-transmit repeater by setting REPE high. In repeater mode data received on link A's receiver is forwarded to link A's transmitter, link B's receiver to link B's transmitter, and so on. The following configuration inputs may be used to control how the repeater handles data that passes through it: 10-bit interface, byte alignment, word synchronization, add/drop idle, half-speed, and double data rate modes. Certain configurations are more effective than others for various applications. The transmitter at the source, the receiver at the destination, and the repeater must have compatible configurations to ensure proper operation. The following sections describe how each configuration control affects repeater operation.
Table 4-3. Settings for Repeater Mode
Mode Word Synchronization Mode Byte Alignment Mode Signals WSE BSYNC_1 Recommended State Don't care Don't care Description Enables word synchronization if desired. See Section 4.4.3 for more details. Byte alignment is required for idle detection. Both alignment modes are supported in repeater mode. See Section 4.4.2 for more details. When enabled, allows the receiver to add/delete idle patterns to maintain word alignment. This is the recommended operating mode. Recovered clock mode cannot be run in repeater mode therefore, add/delete idles must be enabled When enabled, the idle character must be part of the TBI code set. When disabled, the idle is naturally supported by the 8B/10B codes. Recovered clock mode cannot be run in repeater mode. Repeater mode uses reference clock mode exclusively.
Add / Drop Idle Mode
ADIE
High
10-bit Interface
TBIE
Don't care
Recovered Clock
RCCE
Illegal
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4-3
Repeater Mode
Table 4-3. Settings for Repeater Mode (continued)
Mode Half-Speed Enable Double Data Rate Signals HSE DDRE Recommended State Don't care Don't care Description User programmable depending on desired reference clock frequency. See Section 4.4.6 for mode details. User programmable depending on desired reference clock frequency. See Section 4.4.6 for mode details.
4.4.1
10-Bit Interface Mode
When the device is in TBI mode (TBIE = high) the internal 8B/10B encoder and decoder are bypassed and the 10-bit data received is forwarded directly to the transmitter. Running disparity is assumed correct and is not checked. This is important when using disparity-based word synchronization where incorrect running disparity is used as a word synchronization event marker. 10-bit mode must be enabled for disparity-based word alignment to operate properly because it allows the improper disparity to pass through the repeater. When byte interface mode is enabled (TBIE = low), received data is passed through the 8B/10B decoder where it is converted into its eight-bit data or control byte. Running disparity and code validity are checked and reported with the received byte at the receiver interface as described in Section 3.5.4, "Receiver Interface Modes." The decoded byte is re-coded by the transmitter's 8B/10B encoder for transmission. NOTE Byte interface mode must not be used with non-aligned mode or disparity-based word synchronization.
4.4.2
Byte Alignment Mode
The byte alignment mode must be consistent with the transmitter and receiver with which the repeater is being used. All byte alignment modes are supported in repeater mode. When establishing byte alignment for the link through the repeater, the byte alignment sequence must be repeated twice, once for the repeater and once for the destination's receiver. For example, if the byte aligned with realignment mode is enabled (BSYNC_0/BSYNC_1 = high/low), at least eight idle characters must be transmitted, four for repeater alignment and four for the destination's receiver alignment.
4.4.3
Word Synchronization Mode
Word synchronization may be used in repeater mode. This allows the incoming bytes to be synchronized into their corresponding words, removing cable skew from the transmission
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Configuration and Control Signals
source and re-establishing synchronization. All word synchronization modes are supported in repeater mode. Similar to byte alignment, the word synchronization sequence must be repeated twice, once for the repeater and once for the destination's receiver. If the 4 idle/1 non-idle word synchronization event mode is being used, a 4 idle/1 non-idle word synchronization event must be followed by a second 4 idle/1 non-idle word synchronization event to enable the entire link to establish word synchronization. Note that byte alignment must be established prior to word synchronization. See Section 4.4.2, "Byte Alignment Mode," on page 4-4.
4.4.4
Recovered Clock Mode
The MC92600 Quad's four transmitters are timed exclusively to the reference clock domain. Recovered clock mode cannot be used in repeater mode. The setting on the recovered clock enable input, RCCE, is ignored when in repeater mode and all data is timed to the reference clock.
4.4.5
Add/Drop Idle Mode
Repeater mode is timed exclusively to the reference clock domain as stated above. A frequency offset between the source transmitter and the repeater will cause the repeater's receiver to eventually overrun/underrun. To ensure that overrun/underrun does not cause data to be lost, add/drop idle mode must be used. Add/drop idle mode is enabled by setting ADIE high. The repeater adds or drops idles from the data stream to maintain alignment to the reference clock. The guidelines for idle density are discussed in Section 3.4.2, "Reference Clock Timing Mode."
4.4.6
Half-Speed Mode, Double Data Rate Mode
Half-speed mode and double data rate mode simply affect the frequency of the reference clock that must be provided and the timing of the receiver interface. All combinations of these modes are supported in repeater mode. See Section 3.5.4.4, "Half-Speed Mode" for more information on half-speed mode and Section 3.5.4.3, "Double Data Rate Mode" for more information on double data rate mode.
4.5
Configuration and Control Signals
The MC92600 has many configuration and control signals that are asynchronous to all inputs clocks. Most of the signals affect internal configuration state and must be set at power-up. If their state is changed after power-up, some require that the chip be reset by setting RESET low and then releasing high. While other configuration signals are meant to be changed during normal operation and do not require chip reset. However, these signals may still affect device operation. Table 4-4 lists all of the MC92600 asynchronous
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Power Supply Requirements
configuration and control signals and describes the effect of changing their state after power up.
Table 4-4. Asynchronous Configuration and Control Signals
Signal Name TBIE HSE DDRE BSYNC_0 BSYNC_1 ADIE RCCE REPE WSE TST_0, TST_1 LBE Description Ten-Bit Interface Enable Half-Speed Enable Double data rate enable Word Sync. Event Method Byte Alignment Mode Add/Drop Idle Enable Recovered Clock Enable Repeater Mode Enable Word Synchronization Enable Test mode definers Loop Back Enable Effect of Changed State Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Device must be reset. Must be low and remain low during normal operation Receiver must acquire new bit phase alignment; byte and word synchronization must be re-established. Enable/disable transmit links during testing (LBOE = high), no recovery action necessary Receiver must re-establish byte and word synchronization. Device is reset.
LBOE
Loopback Output Enable
STNDBY RESET
Puts PLL Standby mode System Reset Bar
4.6
Power Supply Requirements
The board design should have a minimum of two solid planes of one ounce copper. One plane is to be used as a ground plane and the second plane is to be used for the 1.8V supply. It is recommended that the board has its own 1.8V and 3.3V regulators with less than 50 mV ripple.
4.7
Phase-Locked Loop (PLL) Power Supply Filtering
An analog power supply is required for the internal PLL. The PLLAVDD signal provides power for the analog portions of the PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in Figure 4-1. For maximum effectiveness, the filter circuit is placed as close as possible to the PLLAVDD ball to ensure it filters out as much noise as possible. The ground connection should be near the PLLAGND ball. The 0.01F capacitor is closest to the ball, followed by the 1F
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Decoupling Recommendations
capacitor, and finally the 1 resistor to Vdd on the 1.8V power plane. The capacitors are connected from PLLAVDD to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide and direct.
VDD 1 1 F 0.01 F PLLAVDD
GND
Figure 4-1. PLL Power Supply Filter Circuit
4.8
Decoupling Recommendations
The MC92600 requires a clean, tightly regulated source of power to ensure low jitter on transmit, and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. * Only surface mount technology (SMT) capacitors should be used, to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. The board should have about 10 x 10nF SMT ceramic chip capacitors as close as possible to the 1.8V (Vdd and XVdd) balls of the device. The board should also have about 10 x 10nF SMT ceramic chip capacitors as close as possible to the 3.3V (OVdd) balls of the device. Where the board has blind vias, these capacitors should be placed directly below the MC92600 supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the MC92600, as close to the supply and ground connections as possible. A 1uF ceramic chip capacitor should exist on each side of the MC92600 device. This should be done for both the 1.8V supply and the 3.3V supply. Between the MC92600 device and the voltage regulator should be a 10uF, low equivalent series resistance (ESR) SMT tantalum chip capacitor, and a 100uF, low ESR SMT tantalum chip capacitor. This should be done for both the 1.8V supply and the 3.3V supply.
*
* *
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Decoupling Recommendations
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Chapter 5 Test Features
The MC92600 supports several test modes for in-system built-in self test (BIST) and production testing. Test modes are selected through the TST_0, TST_1, LBE and LBOE signals. Table 5-1 shows test mode state selection.
Table 5-1. Test Mode State Selection
TST_1 Low Low Low Low Low High TST_0 Low Low High High Low Don't care LBE Low High Low High Low Don't care LBOE Low Don't care Don't care Don't care High Don't care Description Normal operation, no test mode enabled Loop back system test mode (Section 5.1) BIST sequence system test mode (Section 5.2) Loop back BIST sequence system test mode (Section 5.3) Board level production test mode (Section 5.4) Reserved
5.1
Loop Back System Test
The MC92600 can be configured in loop back mode where the transmitted data is looped back to its receiver independent of the receiver's link inputs. This is enabled by setting LBE high. The characters transmitted are controlled by the normal transmitter controls. If the transceiver is working properly, the data/control characters transmitted are received by the receiver. This allows system logic to use various data sequences to test the operation of the transceiver. The loop-back signals are electrically isolated from the XLINK_x_P/XLINK_x_N output signals. Therefore, if the outputs are shorted, or otherwise restricted, the loop-back signals still operate normally. When in loop-back mode, the LBOE signal controls the action of the XLINK_x_P/XLINK_x_N output signals. When LBOE is low, the transmit driver holds the XLINK_x_P/XLINK_x_N output signals high and low, respectively. When LBOE is high, the XLINK_x_P/XLINK_x_N output signals continue to operate normally. The receiver's link input signals, RLINK_x_P and RLINK_x_N, are also electrically isolated during loop back mode, such that their state does not affect the loop back path.
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Chapter 5. Test Features
5-1
BIST Sequence System Test Mode
5.2
BIST Sequence System Test Mode
The MC92600 transmitter has an integrated, 23rd order, pseudo-noise (PN) pattern generator. Stimulus from this generator may be used for internal built-in self testing (BIST). The receiver has a 23rd order signature analyzer that is synchronized to the incoming PN stream and may be used to count character mismatch errors relative to the internal PN reference pattern. To properly use the BIST sequence system test mode, the system must provide the proper stimulus in a special sequence. The sequence of steps to run a BIST test is as follows: 1. Select the reference clock frequency at which you wish to run the BIST test. See Table 4-1 , "Legal Reference Clock Frequency Ranges" for pin settings for HSE and DDRE modes. 2. Enter test mode by setting the test mode inputs as described in Table 5-1. 3. Transmit two 4/1 word synchronization event sequences. 4. Transmit to the receiver an 8B/10B encoded PN sequence as described above. The transmitter will automatically go through steps 3 and 4 upon entering this test mode. Upon completion of testing, the transceiver will need to be re-synchronized before normal operation can resume. This implementation of the 23-bit PN generator and analyzer uses the polynomial: f = 1 + x5 + x23 The total mismatch error count is reset to zero when BIST mode is entered. The count is updated continuously while in BIST mode. The value of the count is presented on the receiver interface signals: RECV_x_7 through RECV_x_0, making up the eight-bit error count, ordered bits 7 through 0, respectively. The value of the count is sticky in that the count will not wrap to zero upon overflow, but rather stays at the maximum count value (11111111). The RECV_x_ERR, RECV_x_K and RECV_x_IDLE have special meaning during this test mode. They report the status of the receiver and PN analysis logic. Table 5-2 , "BIST Error Codes" describes the BIST error codes and their meaning.
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Loop Back BIST Sequence System Test Mode
Table 5-2. BIST Error Codes
RECV_x_ERR Low High High High High RECV_x_K Low Low Low High High RECV_x_IDLE Low Low High Low High Description BIST running, no PN mismatch this character. BIST running, PN mismatch error this character. Receiver byte/word synchronized, PN analyzer is not locked. Not byte sync--The receiver is in start-up or has lost byte alignment and is searching for alignment. Not word sync--The receiver is byte synchronized but has not achieved or has lost word alignment and is searching for alignment.
The BIST sequence makes use of the 8B/10B encoder/decoder. Therefore, this test mode overrides the setting on TBIE signal and forces byte interface mode. Additionally, the BIST sequence requires that a normal byte alignment mode be used. The settings on BSYNC_0 and BSYNC_1 are overridden, forcing the device into the byte aligned with realignment mode. In addition to the above signals, the generation of disparity-based word synchronization events is blocked. The WSE_GEN signal is ignored when this test mode is enabled. BIST is run at the speed indicated by the frequency of the reference clock and by the speed range selected by half-speed mode (HSE). The settings of DDRE, WSE and RCCE are not altered and BIST will follow their setting
5.3
Loop Back BIST Sequence System Test Mode
This test mode is the combination of the loop back and BIST sequence system test modes. The device operates as described in Section 5.1, "Loop Back System Test" and Section 5.2, "BIST Sequence System Test Mode." However, the need to go through the start-up sequence is eliminated because the transmitter automatically goes through the proper sequence.
5.4
Board Level Manufacturing Test Mode
In this test mode all TTL output drivers (all data outputs, status outputs, and recovered clock outputs) are placed in a high impedance state to facilitate common board level manufacturing testing practices. Note, however, that the transmitter link output drivers are still active. In normal operational modes (TST_0, TST_1 and LBE all low), LBOE must also be low. If LBOE is high, the transmitters will be functioning properly, however, the receivers will appear to be non-functional because all TTL output drivers are in a high impedance state.
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Board Level Manufacturing Test Mode
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Chapter 6 Electrical Specifications and Characteristics
This chapter explains the electrical specifications and characteristics of the MC92600 device. This chapter consists of the following sections: * * * Section 6.1, "General Characteristics" Section 6.2, "DC Electrical Characteristics" Section 6.3, "AC Electrical Characteristics"
6.1
General Characteristics
This section presents the general technical parameters, the maximum and recommended operating conditions for the MC92600.
6.1.1
General Parameters
0.25m lithography, HiP4 CMOS, 5 layer metal 196 molded plastic ball grid array (MAPBGA), 15mm body size 217 plastic ball grid array (PBGA), 23 mm body size 1.8V + 0.15V dc
The following list provides a summary of the general parameters of the MC92600. Technology Packages: Core power supply
TTL I/O power supply 3.3V + 0.3V dc or 2.5V + 0.2V dc Link I/O power supply 1.8V + 0.15V dc
6.2
DC Electrical Characteristics
The tables in this section describe the MC92600 DC electrical characteristics. Table 6-1 shows the absolute maximum ratings for the MC92600 device.
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6-1
DC Electrical Characteristics
Table 6-1. Absolute Maximum Ratings
Characteristic Core supply voltage PLL supply voltage TTL I/O supply voltage Link I/O supply voltage TTL input voltage Link input voltage Storage temperature range
1
Symbol Vdd AVdd OVdd 1 XVdd Vin Vin Tstg
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55
Max 2.2 2.2 4.0 2.2 OVdd + 0.3 XVdd + 0.3 150
Unit V V V V V V
oC
OVdd must not exceed Vdd/AVdd by more than 2.2V at any time including during power-up.
Functional and tested operating conditions are given in Table 6-2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums are not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
Table 6-2. Recommended Operating Conditions
Characteristic Core Supply Voltage PLL Supply Voltage TTL I/O Supply Voltage Link I/O Supply Voltage TTL Input Voltage Link input voltage Junction temperature - MC92600JUB or MC92600ZTB Junction temperature - MC92600CJUB Ambient temperature 1 - MC92600JUB or MC92600ZTB Ambient temperature1 - MC92600CJUB
1
Symbol Vdd AVdd OVdd XVdd Vin Vin TJ TJ Ta Ta
Min 1.65 1.65 2.3 1.65 0 0 0 -40 0 -40
Max 1.95 1.95 3.6 1.95 OVdd XVdd 105 105 70 70
Unit V V V V V V
oC oC oC oC
Operating Ambient Temperature is dependent on proper thermal management to meet operating Junction Temperature specifications.
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DC Electrical Characteristics
6.2.1
Characteristics of the 3.3V Device
Table 6-3 displays the 3.3V electrical characteristics of the MC92600 device. Voltage symbols of Table 6-3 are defined in Table 6-2Characteristics of the 2.5V Device.
Table 6-3. DC Electrical Specifications for 3.3V Power Supply
Characteristic 1, 2, 3 TTL input high voltage TTL input low voltage TTL input leakage current, Vin = OVdd TTL input leakage current, Vin = GND TTL output high voltage, IOH = -6 mA TTL output low voltage, IOL = 6 mA TTL input capacitance TTL output impedance, Vout = OVdd/2 Link common mode input impedance Link differential input impedance, MEDIA = low/high Link common mode input level Link differential input amplitude Link input capacitance Link common mode output level Link differential output amplitude, 100/150 diff load, MEDIA = low/high Link differential output impedance, MEDIA = low/high Power dissipation: 8B/10B mode Power dissipation: 10 bit mode
1
Symbol VIH VIL IIH IIL VOH VOL Cin Rout Rcm Rdiff Vcm Vin Cin Vcm Vout Rout -- --
Min 2.0 -- -- -- 2.4 -- -- 40 2 85/127.5 0.725 0.4 -- 0.725 1.3 -- -- --
Typical -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100/150 941 4 9694
Max -- 0.8 10 10 -- 0.4 10 62 4 125/180 1.225 3.2 3 1.075 2.2 -- 1098 1130
Unit V V A A V V pF k V Vp-p pF V Vp-p mW mW
Vdd = AVdd = XVdd = 1.8 + 0.15 V dc; OVdd = 3.3 + 0.3 V dc; GND = 0 V dc; 0 < TJ < 105oC for MC92600JUB and MC92600ZTB or -40 < TJ < 105oC for MC92600CJUB 2 These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 3 Recommended supply power-up order is V , AV , OV , XV , however, any order is acceptable as long as dd dd dd dd maximum ratings are not exceeded 4 Simulation-based values. Typical tester values yield 780mW.
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Chapter 6. Electrical Specifications and Characteristics
6-3
AC Electrical Characteristics
Table 6-4 displays the 2.5V electrical characteristics of the MC92600 device. The table's voltage symbols are defined in Table 6-2.
Table 6-4. DC Electrical Specifications for 2.5V Power Supply
Characteristic 1, 2, 3 TTL input high voltage TTL input low voltage TTL input leakage current, Vin = OVdd TTL input leakage current, Vin = GND TTL output high voltage, IOH = -6 mA TTL output low voltage, IOL = 6 mA TTL input capacitance TTL output impedance, Vout = OVdd/2 Link common mode input impedance Link differential input impedance, MEDIA = low/high Link common mode input level Link differential input amplitude Link input capacitance Link common mode output level Link differential output amplitude, 100/150 diff load, MEDIA = low/high Link differential output impedance, MEDIA = low/high Power dissipation: 8B/10B mode Power dissipation: 10 bit mode
1
Symbol VIH VIL IIH IIL VOH VOL Cin Rout Rcm Rdiff Vcm Vin Cin Vcm Vout Rout -- --
Min 1.6 -- -- -- 1.9 -- -- 45 2 85/127.5 0.725 0.4 -- 0.725 1.3 -- -- --
Typical -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100/150 873
4
Max -- 0.8 5 5 -- 0.4 10 70 4 125/180 1.225 3.2 3 1.075 2.2 -- 1014 1055
Unit V V A A V V pF k V Vp-p pF V Vp-p mW mW
889 4 105oC
Vdd = AVdd = XVdd = 1.8 + 0.15 V dc; OVdd = 2.5+ 0.2 V dc; GND = 0 V dc; 0 < TJ < for MC92600JUB and MC92600ZTB or -40 < TJ < 105oC for MC92600CJUB 2 These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 3 Recommended supply power-up order is V , AV , OV , XV , however, any order is acceptable as long as dd dd dd dd maximum ratings are not exceeded. 4 Simulation-based values. Typical tester values yield 780mW.
6.3
6.3.1
AC Electrical Characteristics
Parallel Port Interface Timing
This section describes the AC electrical characteristics of the MC92600 device.
The following figures and tables show the timing for the transmitter and receiver parallel interface.
6-4
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MOTOROLA
AC Electrical Characteristics
6.3.1.1
Transmitter (DDRE = Low)
The transmitter timing diagram for DDRE = Low is shown in Figure 6-1.
REF_CLK XMIT_x_7-0 XMIT_x_K XMIT_x_IDLE_B WSE_GEN T1 T2
Figure 6-1. Transmitter Interface Timing Diagram (DDRE = Low)
Table 6-5 shows the timing specifications for DDRE = Low.
Table 6-5. Transmitter Timing Specification (DDRE = Low)
Symbol T1 T2 Characteristic Setup time to rising edge of REF_CLK Hold time to rising edge of REF_CLK Min 0.5 0.6 Max Unit ns ns
6.3.1.2
Transmitter (DDRE = High)
The transmitter timing diagram for DDRE = High is shown in Figure 6-2.
REF_CLK XMIT_x_7-0 XMIT_x_K XMIT_x_IDLE_B WSE_GEN T1 T2 T1 T2
Figure 6-2. Transmitter Interface Timing Diagram (DDRE = High)
Table 6-6 shows the timing specifications for DDRE = High.
Table 6-6. Transmitter Timing Specification (DDRE = High)
Symbol T1 T2 Characteristic Setup time to rising/falling edge of REF_CLK Hold time to rising/falling edge of REF_CLK Min 0.5 0.6 Max Unit ns ns
6.3.1.3
Receiver (DDRE = Low, RCCE = Low)
The receiver timing diagram for DDRE = Low, RCCE = Low is shown in Figure 6-3.
MOTOROLA
Chapter 6. Electrical Specifications and Characteristics
6-5
AC Electrical Characteristics
REF_CLK RECV_x_7-0 RECV_x_K RECV_x_IDLE RECV_x_ERR RECV_x_9
T1
T2
Tf, Tr
Figure 6-3. Receiver Interface Timing Diagram (DDRE = Low, RCCE = Low)
shows the timing specifications for DDRE = Low, RCCE = Low.
Table 6-7. Receiver Timing Specification (DDRE = Low, RCCE = Low)
Symbol T1 Characteristic Output valid time before rising edge of REF_CLK 1 Output valid time before rising edge of REF_CLK 2 T2 Output valid time after rising edge of REF_CLK1,2, 3 Output valid time after rising edge of REF_CLK1,2, 4 Tf Tr
1 2
Min 3.0 11.0 2.0 1.744 -
Max 1.8 1.8
Unit ns ns ns ns ns ns
Output fall time 5 Output rise time5
Full speed, HSE = Low. Half speed, HSE_High. 3 Operating Junction Temperature, T = 0 to +105 oC J 4 Operating Junction Temperature, T = -40 to +105 oC J 5 10 pF output load.
6.3.1.4
Receiver (DDRE = High, RCCE = Low)
The receiver timing diagram for DDRE = High, RCCE = Low is shown in Figure 6-4.
REF_CLK RECV_x_7-0 RECV_x_K RECV_x_IDLE RECV_x_ERR RECV_x_9
T1
T2
T1
T2
Figure 6-4. Receiver Interface Timing Diagram (DDRE = High, RCCE = Low)
Table 6-8 shows the timing specifications for DDRE = High, RCCE = Low.
6-6
MC92600 SERDES User's Manual
MOTOROLA
AC Electrical Characteristics
)
Table 6-8. Receiver Timing Specification (DDRE = High, RCCE = Low
Characteristic Output valid time before rising/falling edge of REF_CLK 1, 2 Output valid time before rising/falling edge of REF_CLK1, 3 T2 Output valid time after rising/falling edge of REF_CLK2,3, 4 Output valid time after rising/falling edge of REF_CLK2,3, 5 Min 2.2 10.2 2.0 1.744 Max Unit ns ns ns ns
Symbol T1
1 2
REF_CLK duty cycle 45/55. Full speed, HSE = Low. 3 Half speed, HSE = High. 4 Operating Junction Temperature, T = 0 to +105 oC J 5 Operating Junction Temperature, T = -40 to +105 oC J
6.3.1.5
Receiver (DDRE = Low, RCCE = High)
The receiver timing diagram for DDRE = Low, RCCE = High is shown in Figure 6-5.
RECV_x_RCLK RECV_x_7-0 RECV_x_K RECV_x_IDLE RECV_x_ERR RECV_x_9
T1
T2
Figure 6-5. Receiver Interface Timing Diagram (DDRE = Low, RCCE = High
Table 6-9 shows the timing specifications for DDRE = Low, RCCE = High.
Table 6-9. Receiver Timing Specification (DDRE = Low, RCCE = High)
Symbol T1 Characteristic Output valid time before rising edge of RECV_x_RCLK 1 Min 2.5 5.7 3.4 6.6 Max -- -- -- -- Unit ns ns ns ns
T2
Output valid time before rising edge of RECV_x_RCLK 2 Output valid time after rising edge of RECV_x_RCLK1 Output valid time after rising edge of RECV_x_RCLK2
1 2
Full speed, HSE = Low. Half speed, HSE = High.
6.3.1.6
Receiver (DDRE = High, RCCE = High)
The receiver timing diagram for DDRE = High, RCCE = High is shown in Figure 6-6.
MOTOROLA
Chapter 6. Electrical Specifications and Characteristics
6-7
AC Electrical Characteristics
RECV_x_RCLK RECV_x_7-0 RECV_x_K RECV_x_IDLE RECV_x_ERR RECV_x_9
T1
T2
T1
T2
Figure 6-6. Receiver Interface Timing Diagram (DDRE = High, RCCE = High)
Table 6-10 shows the timing specifications for DDRE = High, RCCE = High.
Table 6-10. Receiver Timing Specification (DDRE = High, RCCE = High)
Symbol T1 Characteristic Setup time to rising/falling edge of RECV_x_RCLK 1 Setup time to rising/falling edge of RECV_x_RCLK 2 T2 Hold time to rising/falling edge of RECV_x_RCLK1 Hold time to rising/falling edge of RECV_x_RCLK2
1 2
Min 2.5 5.7 3.4 6.6
Max -
Unit ns ns ns ns
Full speed, HSE = Low. Half speed, HSE = High.
6.3.2
Reference Clock Timing
The timing diagram for the reference clock is shown in Figure 6-7.
REF_CLK
Tf, Tr
TH 1/frange
TL
Figure 6-7. Reference Clock Timing Diagram
Table 6-11 shows the timing specifications for the reference clock.
Table 6-11. Reference Clock Specification
Symbol Tr Tf TH REF_CLK rise time 1 REF_CLK fall time1 Characteristic Min -- -- 3.2 Max 2.0 2.0 -- Unit ns ns ns
REF_CLK pulse width high 2
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MC92600 SERDES User's Manual
MOTOROLA
AC Electrical Characteristics
Table 6-11. Reference Clock Specification (continued)
Symbol TL frange REF_CLK pulse width low2 REF_CLK frequency range 3 REF_CLK frequency range 4 REF_CLK frequency range 5 TD REF_CLK duty cycle 6 REF_CLK duty cycle 7 foffset Tj Tlock
1 2 3 4 5 6 7 8 9
Characteristic
Min 3.2 95 47.5 23.75 40 45 -250 -
Max -- 135 67.5 33.75 60 55 250 80 20,480 + 25 s
Unit ns MHz MHz MHz % % ppm ps bit-times
REF_CLK to REF_CLK frequency offset REF_CLK input jitter 8 PLL lock time 9
Measured between 10-90% points. Measured between 50-50% points. Full speed (HSE = Low), normal data rate (DDRE = Low). Half speed (HSE = High), normal data rate (DDRE = Low); and full speed (HSE = Low), double data rate (DDRE = High). Half speed (HSE = High), double data rate (DDRE = High). Normal data rate (DDRE = Low). Double data rate (DDRE = High). Total peak-to-peak jitter Lock time after compliant REF_CLK signal applied.
6.3.3
Receiver Recovered Clock Timing
The timing diagram for the recovered clock is shown in Figure 6-8.
RECV_x_RCLK
Trck
Tsrck Tf, Tr
Tlrck
Figure 6-8. Recovered Clock Timing Diagram
Table 6-12 shows the timing specifications for the recovered clock.
MOTOROLA
Chapter 6. Electrical Specifications and Characteristics
6-9
AC Electrical Characteristics
Table 6-12. Recovered Clock Specification
Symbol Trck Tsrck Tlrck Tr Tf
1
Characteristic RECV_x_RCLK normal cycle period 1 RECV_x_RCLK short cycle period1
Min 8.0 6.4 9.6 -
Max 1.8 1.8
Unit ns ns ns ns ns
RECV_x_RCLK long cycle period1 RECV_x_RCLK rise time 2
RECV_x_RCLK fall time2
Measured between 50-50% points, 125 MHz REF_CLK, full speed (HSE = Low), normal data rate (DDRE = Low). 2 Measured between 10-90% points.
6.3.4
Serial Data Link Timing
This following sections cover the input and output data link timing.
6.3.4.1
Link Differential Output
The transmitter timing diagram for the link differential output is shown in Figure 6-9.
XLINK_x_P XLINK_x_N
Tf, Tr
Figure 6-9. Link Differential Output Timing Diagram
Table 6-13 shows the timing specifications for the link differential output.
Table 6-13. Link Differential Output Specification
Symbol Tf Tr Tj Tdj Tds Xlat
1 2
Characteristic Link output fall time 1 Link output rise time 1 Total jitter 2 Deterministic jitter 2 Differential skew 2 Transmit latency 3
Min -
Max 200 200 0.24 0.12 25 25
Unit ps ps UI UI ps bit-times
Measured between 10-90% points. Measured between 50-50% points, 125 MHz REF_CLK, 1.25 gigabaud rate. 3 REF_CLK to first bit transmit.
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MOTOROLA
AC Electrical Characteristics
6.3.4.2
Link Differential Input
The receiver timing diagram for the link differential input is shown in Figure 6-10.
RLINK_x_P RLINK_x_N
Tf, Tr
Figure 6-10. Link Differential Input Timing Diagram
Table 6-14 shows the timing specifications for the link differential input.
Table 6-14. Link Differential Input Timing Specification
Symbol Tf Tr Tjtol Tdjtol Tdstol Rlat
1 2
Characteristic Link input fall time 1 Link input rise time1 Total jitter tolerance 2 Deterministic jitter tolerance 2 Differential skew tolerance 2 Receive latency 3
Min 300 300 0.71 0.45 175 -
Max 62
Unit ps ps UI UI ps bit-times
Measured between 10-90% points. Measured between 50-50% points, 125 MHz REF_CLK, 1.25 gigabaud rate. 3 Bit 0 at receiver input to parallel data out.
MOTOROLA
Chapter 6. Electrical Specifications and Characteristics
6-11
AC Electrical Characteristics
6-12
MC92600 SERDES User's Manual
MOTOROLA
Chapter 7 Package Description
The MC92600 is offered in two packages, a 196 MAPBGA and a 217 PBGA. The 196 MAPBGA utilizes an aggressive 1 mm ball pitch and 15 mm body size for application where board space is limited. The 217 PBGA utilizes a standard 1.27 mm ball pitch and 23 mm body size that eases board routing.
7.1
* * * * * *
196 MAPBGA Package Parameter Summary
Package Type--Fine pitch ball grid array Package Outline--15 mm x 15 mm Package Height--1.60 mm Max Number of Balls--196 Ball Pitch--1 mm Ball Diameter--0.45-0.55 mm
7.2
* * * * * *
217 PBGA Package Parameter Summary
Package Type--Plastic ball grid array Package Outline--23 mm x 23 mm Package Height--2.32 mm Max Number of Balls--217 Ball Pitch--1.27 mm Ball Diameter--0.60-0.90 mm
7.3
Nomenclature and Dimensions of the 196 MAPBGA Package
Figure 7-1 provides the bottom surface nomenclature and package outline drawing of the 196 MAPBGA package. Figure 7-2 provides the package dimensions. Figure 7-3 provides a graphic of the package pin signal mappings.
MOTOROLA
Chapter 7. Package Description
7-1
Nomenclature and Dimensions of the 196 MAPBGA Package
Semiconductor Products Sector
COPYRIGHT 1998 MOTOROLA. ALL RIGHTS RESERVED
MECHANICAL OUTLINES DICTIONARY DO NOT SCALE THIS DRAWING D
98ARH98217A PAGE ISSUE O 1128C DATE 28JUL98
X Y
LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA
M
(SHEET 2 OF 2)
DETAIL K
E
4X 0.15
TOP VIEW 13X e S
14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D
M
METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA
13X e
E F G H J K L M N P
S
BOTTOM VIEW
196X
b 0.15 M 0.08 M
3 ZXY Z
VIEW M-M
TITLE CASE NUMBER: STANDARD: REFERENCE:
196 I/O STD MAP BGA, 15 X 15 PKG, 1.00 PITCH
1128C-01 SHEET 1 OF 2
MOTOROLA U, X
Figure 7-1. 196 MAPBGA Nomenclature
7-2
MC92600 SERDES User's Manual
MOTOROLA
Nomenclature and Dimensions of the 196 MAPBGA Package
Semiconductor Products Sector
COPYRIGHT 1998 MOTOROLA. ALL RIGHTS RESERVED
MECHANICAL OUTLINES DICTIONARY DO NOT SCALE THIS DRAWING
98ARH98217A PAGE ISSUE O 1128C DATE 28JUL98
5 0.20 A2 Z
A
196X
A1 Z 4 0.10 Z
DETAIL K
VIEW ROTATED 90 CLOCKWISE
DIM
MIN
MAX
NOTES
A A1 A2 b D E e S
1.25 0.27 1.16 REF 0.45 15.00 BSC 15.00 BSC 1.00 BSC 0.50 BSC
1.60 0.47
1 2
3
DIMENSIONS ARE IN MILLIMETERS. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE.
0.55
4 5
TITLE
196 I/O STD MAP BGA 15 X 15 PKG, 1.00 PITCH
CASE NUMBER: STANDARD: REFERENCE:
1128C-01 SHEET 2 OF 2
MOTOROLA U, X
Figure 7-2. 196 MAPBGA Dimensions
MOTOROLA
Chapter 7. Package Description
7-3
Nomenclature and Dimensions of the 217 MAPBGA Package
.
14 13 12
HSE
11
RESET_B
10
XMIT_ D_7
9
XMIT_ D_5 XMIT_ D_6
8
XMIT_ D_2 XMIT_ D_3
7
XMIT_ C_0 XMIT_ C_1 XMIT_ C_3 XMIT_ C_2
6
XMIT_ C_4 XMIT_ C_5 XMIT_ C_K XMIT_ C_7
5
XMIT_ C_6
4
RECV_ D_ERR
3
RECV_ D_RCLK
2
RECV_ D_K
1
RECV_ D_4
XPADGND REPE RLINK_ XPADVDD D_N
A B C D E F G H J K L M N P
WSE
REF_CLK XMIT_ D_K
ADIE
RECV_ RECV_ XMIT_C_ PADV DD D_9 PADV DD D_2 IDLE_B RECV_ D_5 RECV_ D_7 RECV_ C_2 RECV_ D_6 RECV_ D_0 RECV_ C_4 RECV_ C_9 RECV_ D_3 RECV_ C_0
RLINK_ XPADGND RCCE D_P
STNDBY PADV DD XMIT_ D_1
XMIT_ D_4 XMIT_ D_0
XPADGND XPADVDD XLINK_ XPADVDD DDRE D_N RLINK_ XPADV XLINK_ DD D_P C_P
RECV_ D_IDLE
RECV_ PADV DD C_1 RECV_ C_3 RECV_ C_7 RECV_ C_6 RECV_ C_K
RECV_ XLINK_ XMIT_D_ COREGND/ COREGND/ COREV COREV COREVDD DD DD D_1 C_P IDLE_B PADGND PADGND
RECV_ RLINK_ XLINK_ XPADVDD XPADGND COREVDD COREGND/ COREGND/ COREGND/ COREGND/ COREVDD PADGND PADGND PADGND PADGND C_5 C_N C_N
XPADGND PLLAGND XPADVDD XPADGND COREVDD COREGND/ COREGND/ COREGND/ COREGND/ COREVDD PADV DD RECV_ B_IDLE PADGND PADGND PADGND PADGND RECV_ RLINK_ PLLAVDD PLL_TPA XPADGND COREVDD COREGND/ COREGND/ COREGND/ COREGND/ COREVDD B_RCLK B_N PADGND PADGND PADGND PADGND
RECV_ RLINK_ XLINK_ COREV COREGND/ COREGND/ COREGND/ COREGND/ COREV XPADVDD XPADGND DD B_K DD PADGND PADGND PADGND PADGND B_P B_N RECV_ B_7
RECV_ C_IDLE RECV_ B_ERR
RECV_ C_RCLK RECV_ C_ERR
RECV_ RECV_ PADV DD B_3 B_9 RECV_ B_0 RECV_ B_5 RECV_ B_6
XPADGND XPADVDD XLINK_ A_P
RECV_ XLINK_ COREV DD COREVDD COREVDD COREVDD COREVDD COREVDD B_4 B_P XMIT_ A_4 XMIT_ A_0 XMIT_ B_2 XMIT_ B_3 XMIT_ B_1 XMIT_ B_0 XMIT_ B_7 XMIT_ B_K XMIT_ B_5 XMIT_ B_4
RLINK_ XPADVDD XLINK_ XPADGND TST_1 A_P A_N
RECV_ A_IDLE
RECV_ A_5
RECV_ RECV_ PADV DD PADV DD B_2 B_1 RECV_ A_7 RECV_ A_6 RECV_ A_2 RECV_ A_3 RECV_ A_K RECV_ A_0 RECV_ A_1 RECV_ A_4
RLINK_ XPADVDD BSYNC_1 XPADVDD WSE_GEN PADV DD XMIT_ A_N A_1 XPADGND MEDIA
TBIE TST_0 XMIT_ A_K XMIT_ A_7 XMIT_ A_6 XMIT_ A_5 XMIT_ A_3 XMIT_ A_2
RECV_ XMIT_B_ PADV DD A_9 IDLE_B XMIT_ B_6
LBOE
LBE
BSYNC_0 XMIT_A_ IDLE_B
RECV_ A_ERR
RECV_ A_RCLK
View G-G (Bottom View)
Figure 7-3. 196 MAPBGA Package
7.4
Nomenclature and Dimensions of the 217 MAPBGA Package
Figure 7-4 provides the bottom surface nomenclature and package outline drawing of the 217 MAPBGA package. Figure 7-5 provides the package dimensions. Figure 7-6 provides a graphic of the package pin signal mappings.
7-4
MC92600 SERDES User's Manual
MOTOROLA
Nomenclature and Dimensions of the 217 MAPBGA Package
Semiconductor Products Sector
COPYRIGHT 1997 MOTOROLA. ALL RIGHTS RESERVED
MECHANICAL OUTLINES DICTIONARY DO NOT SCALE THIS DRAWING MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
PAGE ISSUE O
98ASH98017A 1251 DATE 05SEPT97
M
DETAIL K
E E1
0.20
Y
D1 X D 16X e
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U
M
METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA
16X e
3 0.30 M 0.10 M
217X
b
ZXY Z
VIEW M-M
CASE NUMBER: STANDARD: REFERENCE: I 1251-01 SHEET 1 OF 2
TITLE
217 PBGA 23 X 23 PACKAGE
MOTOROLA
Figure 7-4. 217 PBGA Nomenclature
MOTOROLA
Chapter 7. Package Description
7-5
Nomenclature and Dimensions of the 217 MAPBGA Package
Semiconductor Products Sector
COPYRIGHT 1997 MOTOROLA. ALL RIGHTS RESERVED
MECHANICAL OUTLINES DICTIONARY DO NOT SCALE THIS DRAWING
PAGE ISSUE O
98ASH98017A 1251 DATE 05SEPT97
5 0.35 A3 A A2 A1 0.15 Z Z
Z
4
DETAIL K
VIEW ROTATED 90 CLOCKWISE DIM MIN MAX NOTES
A A1 A2 A3 b D D1 E E1 e
1.92 0.50 0.36 REF 1.12 0.60 23.00 19.00 BSC 19.00 23.00 BSC 1.27 BSC
2.32 0.70 1.22 0.90 20.20 20.20
1 2
3
INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. DIMENSIONS ARE IN MILLIMETERS. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER. PARALLEL TO DATUM PLANE Z. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACK-
4 5
TITLE
217 PBGA 23 X 23 PACKAGE
CASE NUMBER: STANDARD: REFERENCE: I
1251-01 SHEET 2 OF 2
MOTOROLA
Figure 7-5. 217 PBGA Dimensions
7-6
MC92600 SERDES User's Manual
MOTOROLA
Nomenclature and Dimensions of the 217 MAPBGA Package
.
17
16
15
14
13
12
XMIT_ D_4 XMIT_ D_5
11
XMIT_ D_2 XMIT_ D_3
10
9
8
7
XMIT_ C_5
6
5
4
3
2
1 A B C D E F G H J K L M N P R T U
XMIT_ COREGND/ COREV DD REF_CLK STNDBY D_7 PADGND
XMIT_ COREV XMIT_ DD C_4 C_1 XMIT_ COREV XMIT_ DD C_3 C_0 XMIT_ COREV XMIT_ DD C_2 D_0
XMIT_ PADV DD RECV_ D_RCLK C_K RECV_ D_7 RECV_ D_K
RECV_ COREV COREGND/ DD PADGND D_6 RECV_ COREGND/ RECV_ D_5 D_3 PADGND RECV_ D_1 RECV_ D_4 RECV_ D_0 RECV_ D_2 RECV_ C_0
XPADVDD
WSE
HSE
RESET_B XMIT_ D_K
DDRE
XMIT_ XMIT_C_ RECV_ IDLE_B D_IDLE C_6 XMIT_ C_7
XPADGND REPE
ADIE
XMIT_ XMIT_ PADV DD D_1 D_6
RECV_ D_ERR
RECV_ D_9
RLINK_ XPADV XMIT_D_ COREGND/ COREGND/ COREGND/ RECV_ COREGND/ COREGND/ DD XPADGND XPADVDD IDLE_B PADGND COREVDD PADGND COREVDD PADGND COREVDD PADGND COREVDD PADGND C_1 D_N RLINK_ XPADV XPADGND RCCE DD D_P XPADGND XPADVDD XLINK_ XPADGND D_N RLINK_ XPADVDD XLINK_ C_ P D_P XLINK_ C_ P
COREGND/ COREGND/ COREGND/ PADGND PADGND PADGND COREGND/ COREGND/ COREGND/ PADGND PADGND PADGND COREGND/ COREGND/ COREGND/ PADGND PADGND PADGND
PADV DD RECV_ C_3
COREGND/ RECV_ PADGND C_7
RECV_ PADV DD C_2 RECV_ C_4 RECV_ C_5 RECV_ C_K
COREVDD PADV DD RECV_ C_6
COREGND/ RECV_ PADGND C_ERR
RLINK_ XLINK_ XPADVDD XPADGND C_N C_N XPADGND PLLAGND XPADVDD XPADGND RLINK_ PLLAVDD PLL_TPA XPADVDD B_N RLINK_ XLINK_ XPADVDD XPADGND B_P B_N XPADGND XPADVDD XLINK_ A_P XLINK_ B_P
RECV_ RECV_ C_9 C_RCLK
COREVDD RECV_ B_9
RECV_ B_ERR
RECV_ C_IDLE RECV_ B_IDLE
RECV_ B_K RECV_ B_6
RECV_ COREGND/ PADV DD B_RCLK PADGND
COREVDD RECV_ B_5 COREGND/ RECV_ PADGND B_2 RECV_ A_4 RECV_ B_7 RECV_ B_4
RLINK_ XPADV XLINK_ DD A_N XPADGND A_P RLINK_ XPADV XPADGND COREGND/ LBOE DD PADGND A_N XPADGND MEDIA COREGND/ PADGND XPADGND COREGND/ PADGND
TBIE LBE
RECV_ PADV RECV_ DD B_3 A_0 RECV_ B_0 RECV_ B_1
COREGND/ COREV COREGND/ COREV COREGND/ COREV COREGND/ PADV COREGND/ RECV_ DD PADGND DD PADGND DD PADGND DD PADGND PADGND A_3 XMIT_ A_6 XMIT_ A_5 XMIT_ COREVDD XMIT_ A_3 B_0 XMIT_ COREV XMIT_ DD B_1 A_2 XMIT_ XMIT_ COREVDD A_1 A_0 XMIT_ B_2 XMIT_ B_4 XMIT_ B_3 XMIT_ B_6 XMIT_ B_7 XMIT_ B_5
BSYNC_0 WSE_GEN
XMIT_ A_7
RECV_ A_ERR
RECV_ A_IDLE
RECV_ PADV RECV_ DD A_1 A_5 RECV_ A_7 RECV_ A_6 RECV_ A_2
XMIT_A_ XMIT_ A_K IDLE_B
XMIT_B_ RECV_ A_9 IDLE_B
XMIT_ B_K
COREGND/ COREV BSYNC_1 TST_0 DD PADGND
TST_1 PADV DD XMIT_ A_4
RECV_ A_RCLK
RECV_ COREV COREGND/ DD PADGND A_K
View M-M (Bottom View)
Figure 7-6. 217 PBGA Package
MOTOROLA
Chapter 7. Package Description
7-7
Package Thermal Characteristics
7.5 Package Thermal Characteristics
Thermal values for the 196 MAPBGA and 217 PBGA are listed below in Table 7-1. The values listed below assume the customer will be mounting these packages on a thermally enhanced mother board. This is defined as a minimum 4-layer board with one ground plane. The values listed below were measured in accordance with established JEDEC (Joint Electron Device Engineering Council) standards.
Table 7-1. MC92600 Package Option Thermal Resistance Values
Symbol Description Thermal resistance from junction to ambient, still air 196 MAPBGA 38 217 PBGA 26.5
o
Units
ja-0 ja-2 ja-4
1
CW
Thermal resistance from junction to ambient, 200 LFM 1
34
25.1
o
CW
Thermal resistance from junction to ambient, 400 LFM1
33
23.6
o
CW
Linear feet per minute
7.6 MC92600 Chip Pinout Listing
The MC92600 is offered in two packages, a 196 MAPBGA and a 217 PBGA package. Table 7-2 list the MC92600 signal to ball location mapping for the 196 MAPBGA and 217 PBGA package. Also shown are signaling direction (input or output), and the type of logic interface.
Table 7-2. Signal to Ball Mapping for 196 MAPBGA and 217 PBGA Packages
Signal Name Description Ball Number (196 MAPBGA) L8 M8 P8 N8 L9 P9 N9 P10 Ball Number (217 PBGA) U8 U10 T10 R10 U11 T11 R11 T12 Direction I/O Type
XMIT_A_0 XMIT_A_1 XMIT_A_2 XMIT_A_3 XMIT_A_4 XMIT_A_5 XMIT_A_6 XMIT_A_7
Transmitter A, data bit 0 Transmitter A, data bit 1 Transmitter A, data bit 2 Transmitter A, data bit 3 Transmitter A, data bit 4 Transmitter A, data bit 5 Transmitter A, data bit 6 Transmitter A, data bit 7
Input Input Input Input Input Input Input Input
TTL TTL TTL TTL TTL TTL TTL TTL
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Table 7-2. Signal to Ball Mapping for 196 MAPBGA and 217 PBGA Packages
Signal Name Description Ball Number (196 MAPBGA) N10 P11 M1 N1 M2 N2 P1 M5 M3 M4 P2 N3 L5 P4 P3 L14 M14 K12 L12 P7 N7 L7 M7 P6 N6 P5 L6 M6 N5 Ball Number (217 PBGA) T13 T14 N3 R1 T1 P3 N4 R3 T2 T3 U3 T4 R4 R5 U4 N17 P17 M15 N15 R8 T8 R7 U7 T7 U6 R6 T6 U5 T5 Direction I/O Type
XMIT_A_K XMIT_A_IDLE RECV_A_0 RECV_A_1 RECV_A_2 RECV_A_3 RECV_A_4 RECV_A_5 RECV_A_6 RECV_A_7 RECV_A_K RECV_A_9 RECV_A_IDLE RECV_A_ERR RECV_A_RCLK RLINK_A_P RLINK_A_N XLINK_A_P XLINK_A_N XMIT_B_0 XMIT_B_1 XMIT_B_2 XMIT_B_3 XMIT_B_4 XMIT_B_5 XMIT_B_6 XMIT_B_7 XMIT_B_K XMIT_B_IDLE
Transmitter A, special character (data bit 8 for TBI mode) Transmitter A, idle enable bar, (data bit 9 for TBI mode) Receiver A, data bit 0 Receiver A, data bit 1 Receiver A, data bit 2 Receiver A, data bit 3 Receiver A, data bit 4 Receiver A, data bit 5 Receiver A, data bit 6 Receiver A, data bit 7 Receiver A, special character (data bit 8 for TBI mode) Receiver A, data bit 9 for TBI mode Receiver A, idle detect Receiver A, error detect Receiver A, receive data clock Receiver A, positive link input Receiver A, negative link input Transmitter A, positive link out Transmitter A, negative link out Transmitter B, data bit 0 Transmitter B, data bit 1 Transmitter B, data bit 2 Transmitter B, data bit 3 Transmitter B, data bit 4 Transmitter B, data bit 5 Transmitter B, data bit 6 Transmitter B, data bit 7 Transmitter B, special character (data bit 8 for TBI mode) Transmitter B, idle enable bar, (data bit 9 for TBI mode)
Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Output Output Input Input Input Input Input Input Input Input Input Input
TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Link Link Link Link TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL
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Table 7-2. Signal to Ball Mapping for 196 MAPBGA and 217 PBGA Packages
Signal Name Description Ball Number (196 MAPBGA) K3 L4 L1 J3 K4 K2 K1 H3 J4 J1 G3 H2 H4 J14 H14 K11 J11 A7 B7 D7 C7 A6 B6 A5 D6 C6 B5 C1 D2 D4 Ball Number (217 PBGA) P2 P1 M3 N1 M2 L3 M1 L2 L1 J3 K1 J2 K2 L17 K17 M14 L14 B10 A10 C8 B8 A8 A7 B7 C7 A6 B6 D1 D3 E2 Direction I/O Type
RECV_B_0 RECV_B_1 RECV_B_2 RECV_B_3 RECV_B_4 RECV_B_5 RECV_B_6 RECV_B_7 RECV_B_K RECV_B_9 RECV_B_IDLE RECV_B_ERR RECV_B_RCLK RLINK_B_P RLINK_B_N XLINK_B_P XLINK_B_N XMIT_C_0 XMIT_C_1 XMIT_C_2 XMIT_C_3 XMIT_C_4 XMIT_C_5 XMIT_C_6 XMIT_C_7 XMIT_C_K XMIT_C_IDLE RECV_C_0 RECV_C_1 RECV_C_2
Receiver B, data bit 0 Receiver B, data bit 1 Receiver B, data bit 2 Receiver B, data bit 3 Receiver B, data bit 4 Receiver B, data bit 5 Receiver B, data bit 6 Receiver B, data bit 7 Receiver B, special character (data bit 8 for TBI mode) Receiver B, data bit 9 for TBI mode Receiver B, idle detect Receiver B, error detect Receiver B, receive data clock Receiver B, positive link input Receiver B, negative link input Transmitter B, positive link out Transmitter B, negative link out Transmitter C, data bit 0 Transmitter C, data bit 1 Transmitter C, data bit 2 Transmitter C, data bit 3 Transmitter C, data bit 4 Transmitter C, data bit 5 Transmitter C, data bit 6 Transmitter C, data bit 7 Transmitter C, special character (data bit 8 for TBI mode) Transmitter C, idle enable bar, (data bit 9 for TBI mode) Receiver C, data bit 0 Receiver C, data bit 1 Receiver C, data bit 2
Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Output Output Input Input Input Input Input Input Input Input Input Input Output Output Output
TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Link Link Link Link TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL
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Table 7-2. Signal to Ball Mapping for 196 MAPBGA and 217 PBGA Packages
Signal Name Description Ball Number (196 MAPBGA) E2 E3 F4 E1 F2 F1 F3 G2 H1 G1 E14 F14 E11 F11 D8 C8 A8 B8 D9 A9 B9 A10 B10 E9 D3 E4 B1 C2 A1 C5 Ball Number (217 PBGA) E3 F2 F1 G2 F3 G1 H2 J1 H3 H1 G17 H17 G14 H14 C10 C11 A11 B11 A12 B12 C13 A13 B13 D13 D2 C3 C1 B1 C2 B3 Direction I/O Type
RECV_C_3 RECV_C_4 RECV_C_5 RECV_C_6 RECV_C_7 RECV_C_K RECV_C_9 RECV_C_IDLE RECV_C_ERR RECV_C_RCLK RLINK_C_P RLINK_C_N XLINK_C_P XLINK_C_N XMIT_D_0 XMIT_D_1 XMIT_D_2 XMIT_D_3 XMIT_D_4 XMIT_D_5 XMIT_D_6 XMIT_D_7 XMIT_D_K XMIT_D_IDLE RECV_D_0 RECV_D_1 RECV_D_2 RECV_D_3 RECV_D_4 RECV_D_5
Receiver C, data bit 3 Receiver C, data bit 4 Receiver C, data bit 5 Receiver C, data bit 6 Receiver C, data bit 7 Receiver C, special character (data bit 8 for TBI mode) Receiver C, data bit 9 for TBI mode Receiver C, idle detect Receiver C, error detect Receiver C, receive data clock Receiver C, positive link input Receiver C, negative link input Transmitter C, positive link out Transmitter C, negative link out Transmitter D, data bit 0 Transmitter D, data bit 1 Transmitter D, data bit 2 Transmitter D, data bit 3 Transmitter D, data bit 4 Transmitter D, data bit 5 Transmitter D, data bit 6 Transmitter D, data bit 7 Transmitter D, special character (data bit 8 for TBI mode) Transmitter D, idle enable bar, (data bit 9 for TBI mode) Receiver D, data bit 0 Receiver D, data bit 1 Receiver D, data bit 2 Receiver D, data bit 3 Receiver D, data bit 4 Receiver D, data bit 5
Output Output Output Output Output Output Output Output Output Output Input Input Output Output Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output
TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Link Link Link Link TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL
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Table 7-2. Signal to Ball Mapping for 196 MAPBGA and 217 PBGA Packages
Signal Name Description Ball Number (196 MAPBGA) C3 C4 A2 B3 D5 A4 A3 C14 B14 E12 D12 N12 A12 D10 P12 M12 C11 A13 C12 B11 N13 B12 M10 H12 N11 L10 P13 P14 C10 A11 Ball Number (217 PBGA) A3 B4 C4 C5 B5 C6 A4 E17 D17 G15 F15 T15 B15 C14 R13 U15 C15 C16 E14 A15 R16 B16 R12 K15 U14 U13 R14 P13 A14 B14 Direction I/O Type
RECV_D_6 RECV_D_7 RECV_D_K RECV_D_9 RECV_D_IDLE RECV_D_ERR RECV_D_RCLK RLINK_D_P RLINK_D_N XLINK_D_P XLINK_D_N TBIE HSE DDRE BSYNC_0 BSYNC_1 ADIE REPE RCCE REF_CLK MEDIA WSE WSE_GEN PLL_TPA TST_0 TST_1 LBE LBOE STNDBY RESET
Receiver D, data bit 6 Receiver D, data bit 7 Receiver D, special character (data bit 8 for TBI mode) Receiver D, data bit 9 for TBI mode Receiver D, idle detect Receiver D, error detect Receiver D, receive data clock Receiver D, positive link input Receiver D, negative link input Transmitter D, positive link out Transmitter D, negative link out 10-bit interface enable Half speed enable Double data rate enable Byte synchronization mode Select 0 Byte synchronization mode select 1 Add/Drop idle enable Repeater mode enable Recovered clock enable Reference clock Media impedance select Word synchronization enable Generate word synchronization event PLL analog test point Test mode select 0 Test mode select 1 Loop back enable Loop back output enable Standby mode enable System reset bar
Output Output Output Output Output Output Output Input Input Output Output Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input Input Input Input Input
TTL TTL TTL TTL TTL TTL TTL Link Link Link Link TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Analog TTL TTL TTL TTL TTL TTL
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Table 7-2. Signal to Ball Mapping for 196 MAPBGA and 217 PBGA Packages
Signal Name Description Ball Number (196 MAPBGA) E5, E6, F5, G5, H5, J5, K5, K6, K7, K8, K9, K10, J10, H10, G10, F10, E10 E7, E8, F6, F7, F8, F9, H6, H7, H8, H9, G6, G7, G8, G9, J6, J7, J8, J9 Ball Number (217 PBGA) P9, P7, D9, A2, A9, B9, U9, T9, C9, R9, U16, U2, P11, L4, J4, G4, D11, D7, D5, A16 P14, R15, U17, U1, T16, P12, P10, P8, P6, P4, M4, K10, K9, K8, K4, J10, J9, J8, H10, H9, H8, H4, F4, D12, D10, D8, D6, D4, B2, A17, A1 K16 J16 Direction I/O Type
COREVDD
Core logic supply
Vdd
Supply
COREGND/PADGN D
Core logic ground / TTL I/O ground
GND
Ground
PLLAVDD PLLAGND PADVDD
PLL analog supply PLL analog ground TTL I/O supply
H13 G13
AVdd GND OVdd
Supply Ground Supply
B2, D1, G4, E4,E1, G3, J2, L2, L3, N4, K3, N2, R2, M9, C9, B4 P5, U12, C12, A5 L13, K13, G12, E13, D11, D13, M11, M13, J13, F13, B13 N16, M16, J15, G16, F16, B17, K14, L16, D16, E16, H16, P16, D14 M17, L15, J14, H15, F17, E15, N14, R17, J17, F14, C17, P15, T17, D15
XPADVDD
Link I/O supply
XVdd
Supply
XPADGND
Link I/O Ground
K14, J12, G11, F12, D14, N14, L11, G14, A14, H11, C13
GND
Ground
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Appendix A Ordering Information
Figure A-1 provides the Motorola part numbering nomenclature for the MC92600 SERDES. For product availability, contact your local Motorola Semiconductor sales representative.
MC92600xxxB
Product Version Product Code: MC = production product Part Identifier Package: ZT = 196 pin MAPBGA JU = 217 pin PBGA Operating Temperature Range: no code = TJ of 0 to +105 oC C = TJ of -40 to +105 oC
Figure A-1. Motorola Part Number Key
MOTOROLA
Appendix A. Ordering Information
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Appendix B 8B/10B Coding Scheme
The MC92600 provides fibre channel-specific 8B/10B encoding and decoding based on the FC-1 fibre channel standard. Given 8 bits entering a channel, the 8B/10B encoding converts them to 10 bits thereby increasing the transition density of the serially transmitted signal.
B.1 Overview
The FC-1 standard applies an algorithm that ensures that no more than five 1's or 0's are transmitted consecutively, giving a transition density equal to 2.5 for each 10 bit data block. Such a density ensures proper DC balance across the link and is sufficient for good clock recovery. In the 8B/10B notation scheme, bytes are referred to as transmission characters, and each bit is represented by letters. Unencoded bits, the 8 bits that have not passed through a 8B/10B encoder, are represented by letters "A" through "H", which are bits 0 through7.
One unencoded transmission character (Byte) H Bit 7 G Bit 6 F Bit 5 E Bit 4 D Bit 3 C Bit 2 B Bit 1 A Bit 0 lsb
Figure B-1. Unencoded Transmission Character Bit Ordering
Encoded bits, those that have passed through an encoder, are represented with the letters "a" through "j", representing bits 0-9 respectively. Character (bit) ordering in the fibre channel nomenclature is little-endian, with "a" being the least significant bit in a byte.
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-1
Overview
One coded transmission character (Byte) j Bit 9 h Bit 8 g Bit 7 f Bit 6 i Bit 5 e Bit 4 d Bit 3 c Bit 2 b Bit 1 a Bit 0 lsb
Figure B-2. Encoded Transmission Character Bit Ordering
B.1.1 Naming Transmission Characters
Transmission characters are given names based on the type of data in the byte and the bit values of the character. Two types of transmission characters are specified: data and special. Data characters are labeled "D" characters and special characters are labeled "K" characters. Each transmission character has a bit value and a corresponding decimal value. These elements are combined to provide each character with a name, see Table B-1.
Table B-1. Components of a Character Name
HGF 001 1 D or K EDCBA 11100 28 8B/10B notation Data bit value Decimal value of the bit value Kind of transmission character
D28.1 = Data name assigned to this data byte if it is a data character. K28.1 = Data name assigned to this data byte if it is a special character.
B.1.2 Encoding
Following is a simplified sequence of steps in 8B/10B coding: 1. An 8-bit block of unencoded data (a transmission character) is picked up by a transmitter. 2. The transmission character is broken into sub-blocks of three bits and five bits. The letters H G and F comprise the 3-bit block, and the letters E D C B and A comprise the 5-bit block. 3. The 3-bit and 5-bit sub-blocks pass through a 3B/4B encoder and a 5B/6B encoder, respectively. A bit is added to each sub-block, such that the transmission character is encoded and expanded to a total of 10-bits. 4. At the time the character is expanded into 10 bits, it is also encoded into the proper running disparity, either positive (RD+) or negative (RD-) depending on certain calculations (see Section B.1.3, "Calculating Running Disparity"). At start-up, the transmitter assumes negative running disparity.
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Data Tables
5. The positive or negative disparity transmission character (see Figure B-3) is passed to the transmit driver, available for differentialization (See Section 2.5.2, "Transmit Driver Operation").
J H G F I E D C B A
Direction of Transmission
Figure B-3. Character Transmission
B.1.3 Calculating Running Disparity
Running disparity improves error detection and recovery. The rules for calculating the running disparity for sub-blocks are as follows (reference Fibre Channel, Gigabit Communications and I/O for Computer Networks): * Running disparity at the end of any sub-block is positive if (1) the encoded sub-block contains more 1s than 0s, (2) if the 6-bit sub-block is 6'b00 0111, or (3) if the 4-bit sub-block is 4'b0011. Running disparity at the end of any sub-block is negative if (1) the encoded sub-block contains more 0 than 1 bits, (2) if the 6-bit sub-block is 6'b11 1000, or (3) if the 4-bit sub-block is 4'b1100. Otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block.
*
*
B.2 Data Tables
Table B-2 displays the full valid data character 8B/10B codes. The values in the "Data Value HGFEDCBA" column are the possible bit values of the unencoded transmission characters. The current RD values are the possible positive and negative running disparity values.
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-3
Data Tables
Table B-2. Valid Data Characters
Data Name D0.0 D1.0 D2.0 D3.0 D4.0 D5.0 D6.0 D7.0 D8.0 D9.0 D10.0 D11.0 D12.0 D13.0 D14.0 D15.0 D16.0 D17.0 D18.0 D19.0 D20.0 D21.0 D22.0 D23.0 D24.0 D25.0 D26.0 D27.0 D28.0 D29.0 D30.0 D31.0 D0.2 Data Value
HGF EDCBA
Current RDabcdei fghj 100111 0100 011101 0100 101101 0100 110001 1011 110101 0100 101001 1011 011001 1011 111000 1011 111001 0100 100101 1011 010101 1011 110100 1011 001101 1011 101100 1011 011100 1011 010111 0100 011011 0100 100011 1011 010011 1011 110010 1011 001011 1011 101010 1011 011010 1011 111010 0100 110011 0100 100110 1011 010110 1011 110110 0100 001110 1011 101110 0100 011110 0100 101011 0100 100111 0101
Current RD+ abcdei fghj 011000 1011 100010 1011 010010 1011 110001 0100 001010 1011 101001 0100 011001 0100 000111 0100 000110 1011 100101 0100 010101 0100 110100 0100 001101 0100 101100 0100 011100 0100 101000 1011 100100 1011 100011 0100 010011 0100 110010 0100 001011 0100 101010 0100 011010 0100 000101 1011 001100 1011 100110 0100 010110 0100 001001 1011 001110 0100 010001 1011 100001 1011 010100 1011 011000 0101
Data Name D0.1 D1.1 D2.1 D3.1 D4.1 D5.1 D6.1 D7.1 D8.1 D9.1 D10.1 D11.1 D12.1 D13.1 D14.1 D15.1 D16.1 D17.1 D18.1 D19.1 D20.1 D21.1 D22.1 D23.1 D24.1 D25.1 D26.1 D27.1 D28.1 D29.1 D30.1 D31.1 D0.3
Data Value
HGF EDCBA
Current RDabcdei fghj 100111 1001 011101 1001 101101 1001 110001 1001 110101 1001 101001 1001 011001 1001 111000 1001 111001 1001 100101 1001 010101 1001 110100 1001 001101 1001 101100 1001 011100 1001 010111 1001 011011 1001 100011 1001 010011 1001 110010 1001 001011 1001 101010 1001 011010 1001 111010 1001 110011 1001 100110 1001 010110 1001 110110 1001 001110 1001 101110 1001 011110 1001 101011 1001 100111 0011
Current RD+ abcdei fghj 011000 1001 100010 1001 010010 1001 110001 1001 001010 1001 101001 1001 011001 1001 000111 1001 000110 1001 100101 1001 010101 1001 110100 1001 001101 1001 101100 1001 011100 1001 101000 1001 100100 1001 100011 1001 010011 1001 110010 1001 001011 1001 101010 1001 011010 1001 000101 1001 001100 1001 100110 1001 010110 1001 001001 1001 001110 1001 010001 1001 100001 1001 010100 1001 011000 1100
000 00000 000 00001 000 00010 000 00011 000 00100 000 00101 000 00110 000 00111 000 01000 000 01001 000 01010 000 01011 000 01100 000 01101 000 01110 000 01111 000 10000 000 10001 000 10010 000 10011 000 10100 000 10101 000 10110 000 10111 000 11000 000 11001 000 11010 000 11011 000 11100 000 11101 000 11110 000 11111 010 00000
001 00000 001 00001 001 00010 001 00011 001 00100 001 00101 001 00110 001 00111 001 01000 001 01001 001 01010 001 01011 001 01100 001 01101 001 01110 001 01111 001 10000 001 10001 001 10010 001 10011 001 10100 001 10101 001 10110 001 10111 001 11000 001 11001 001 11010 001 11011 001 11100 001 11101 001 11110 001 11111 011 00000
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Data Tables
Table B-2. Valid Data Characters (continued)
Data Name D1.2 D2.2 D3.2 D4.2 D5.2 D6.2 D7.2 D8.2 D9.2 D10.2 D11.2 D12.2 D13.2 D14.2 D15.2 D16.2 D17.2 D18.2 D19.2 D20.2 D21.2 D22.2 D23.2 D24.2 D25.2 D26.2 D27.2 D28.2 D29.2 D30.2 D31.2 D0.4 D1.4 Data Value
HGF EDCBA
Current RDabcdei fghj 011101 0101 101101 0101 110001 0101 110101 0101 101001 0101 011001 0101 111000 0101 111001 0101 100101 0101 010101 0101 110100 0101 001101 0101 101100 0101 011100 0101 010111 0101 011011 0101 100011 0101 010011 0101 110010 0101 001011 0101 101010 0101 011010 0101 111010 0101 110011 0101 100110 0101 010110 0101 110110 0101 001110 0101 101110 0101 011110 0101 101011 0101 100111 0010 011101 0010
Current RD+ abcdei fghj 100010 0101 010010 0101 110001 0101 001010 0101 101001 0101 011001 0101 000111 0101 000110 0101 100101 0101 010101 0101 110100 0101 001101 0101 101100 0101 011100 0101 101000 0101 100100 0101 100011 0101 010011 0101 110010 0101 001011 0101 101010 0101 011010 0101 000101 0101 001100 0101 100110 0101 010110 0101 001001 0101 001110 0101 010001 0101 100001 0101 010100 0101 011000 1101 100010 1101
Data Name D1.3 D2.3 D3.3 D4.3 D5.3 D6.3 D7.3 D8.3 D9.3 D10.3 D11.3 D12.3 D13.3 D14.3 D15.3 D16.3 D17.3 D18.3 D19.3 D20.3 D21.3 D22.3 D23.3 D24.3 D25.3 D26.3 D27.3 D28.3 D29.3 D30.3 D31.3 D0.5 D1.5
Data Value
HGF EDCBA
Current RDabcdei fghj 011101 0011 101101 0011 110001 1100 110101 0011 101001 1100 011001 1100 111000 1100 111001 0011 100101 1100 010101 1100 110100 1100 001101 1100 101100 1100 011100 1100 010111 0011 011011 0011 100011 1100 010011 1100 110010 1100 001011 1100 101010 1100 011010 1100 111010 0011 110011 0011 100110 1100 010110 1100 110110 0011 001110 1100 101110 0011 011110 0011 101011 0011 100111 1010 011101 1010
Current RD+ abcdei fghj 100010 1100 010010 1100 110001 0011 001010 1100 101001 0011 011001 0011 000111 0011 000110 1100 100101 0011 010101 0011 110100 0011 001101 0011 101100 0011 011100 0011 101000 1100 100100 1100 100011 0011 010011 0011 110010 0011 001011 0011 101010 0011 011010 0011 000101 1100 001100 1100 100110 0011 010110 0011 001001 1100 001110 0011 010001 1100 100001 1100 010100 1100 011000 1010 100010 1010
010 00001 010 00010 010 00011 010 00100 010 00101 010 00110 010 00111 010 01000 010 01001 010 01010 010 01011 010 01100 010 01101 010 01110 010 01111 010 10000 010 10001 010 10010 010 10011 010 10100 010 10101 010 10110 010 10111 010 11000 010 11001 010 11010 010 11011 010 11100 010 11101 010 11110 010 11111 100 00000 100 00001
011 00001 011 00010 011 00011 011 00100 011 00101 011 00110 011 00111 011 01000 011 01001 011 01010 011 01011 011 01100 011 01101 011 01110 011 01111 011 10000 011 10001 011 10010 011 10011 011 10100 011 10101 011 10110 011 10111 011 11000 011 11001 011 11010 011 11011 011 11100 011 11101 011 11110 011 11111 101 00000 101 00001
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-5
Data Tables
Table B-2. Valid Data Characters (continued)
Data Name D2.4 D3.4 D4.4 D5.4 D6.4 D7.4 D8.4 D9.4 D10.4 D11.4 D12.4 D13.4 D14.4 D15.4 D16.4 D17.4 D18.4 D19.4 D20.4 D21.4 D22.4 D23.4 D24.4 D25.4 D26.4 D27.4 D28.4 D29.4 D30.4 D31.4 D0.6 D1.6 D2.6 Data Value
HGF EDCBA
Current RDabcdei fghj 101101 0010 110001 1101 110101 0010 101001 1101 011001 1101 111000 1101 111001 0010 100101 1101 010101 1101 110100 1101 001101 1101 101100 1101 011100 1101 010111 0010 011011 0010 100011 1101 010011 1101 110010 1101 001011 1101 101010 1101 011010 1101 111010 0010 110011 0010 100110 1101 010110 1101 110110 0010 001110 1101 101110 0010 011110 0010 101011 0010 100111 0110 011101 0110 101101 0110
Current RD+ abcdei fghj 010010 1101 110001 0010 001010 1101 101001 0010 011001 0010 000111 0010 000110 1101 100101 0010 010101 0010 110100 0010 001101 0010 101100 0010 011100 0010 101000 1101 100100 1101 100011 0010 010011 0010 110010 0010 001011 0010 101010 0010 011010 0010 000101 1101 001100 1101 100110 0010 010110 0010 001001 1101 001110 0010 010001 1101 100001 1101 010100 1101 011000 0110 100010 0110 010010 0110
Data Name D2.5 D3.5 D4.5 D5.5 D6.5 D7.5 D8.5 D9.5 D10.5 D11.5 D12.5 D13.5 D14.5 D15.5 D16.5 D17.5 D18.5 D19.5 D20.5 D21.5 D22.5 D23.5 D24.5 D25.5 D26.5 D27.5 D28.5 D29.5 D30.5 D31.5 D0.7 D1.7 D2.7
Data Value
HGF EDCBA
Current RDabcdei fghj 101101 1010 110001 1010 110101 1010 101001 1010 011001 1010 111000 1010 111001 1010 100101 1010 010101 1010 110100 1010 001101 1010 101100 1010 011100 1010 010111 1010 011011 1010 100011 1010 010011 1010 110010 1010 001011 1010 101010 1010 010101 1010 111010 1010 110011 1010 100110 1010 010110 1010 110110 1010 001110 1010 101110 1010 011110 1010 101011 1010 100111 0001 011101 0001 101101 0001
Current RD+ abcdei fghj 010010 1010 110001 1010 001010 1010 101001 1010 011001 1010 000111 1010 000110 1010 100101 1010 010101 1010 110100 1010 001101 1010 101100 1010 011100 1010 101000 1010 100100 1010 100011 1010 010011 1010 110010 1010 001011 1010 101010 1010 011010 1010 000101 1010 001100 1010 100110 1010 010110 1010 001001 1010 001110 1010 010001 1010 100001 1010 010100 1010 011000 1110 100010 1110 010010 1110
100 00010 100 00011 100 00100 100 00101 100 00110 100 00111 100 01000 100 01001 100 01010 100 01011 100 01100 100 01101 100 01110 100 01111 100 10000 100 10001 100 10010 100 10011 100 10100 100 10101 100 10110 100 10111 100 11000 100 11001 100 11010 100 11011 100 11100 100 11101 100 11110 100 11111 110 00000 110 00001 110 00010
101 00010 101 00011 101 00100 101 00101 101 00110 101 00111 101 01000 101 01001 101 01010 101 01011 101 01100 101 01101 101 01110 101 01111 101 10000 101 10001 101 10010 101 10011 101 10100 101 10101 101 10110 101 10111 101 11000 101 11001 101 11010 101 11011 101 11100 101 11101 101 11110 101 11111 111 00000 111 00001 111 00010
B-6
MC92600 SERDES User's Manual
MOTOROLA
Data Tables
Table B-2. Valid Data Characters (continued)
Data Name D3.6 D4.6 D5.6 D6.6 D7.6 D8.6 D9.6 D10.6 D11.6 D12.6 D13.6 D14.6 D15.6 D16.6 D17.6 D18.6 D19.6 D20.6 D21.6 D22.6 D23.6 D24.6 D25.6 D26.6 D27.6 D28.6 D29.6 D30.6 D31.6 Data Value
HGF EDCBA
Current RDabcdei fghj 110001 0110 110101 0110 101001 0110 011001 0110 111000 0110 111001 0110 100101 0110 010101 0110 110100 0110 001101 0110 101100 0110 011100 0110 010111 0110 011011 0110 100011 0110 010011 0110 110010 0110 001011 0110 101010 0110 011010 0110 111010 0110 110011 0110 100110 0110 010110 0110 110110 0110 001110 0110 101110 0110 011110 0110 101011 0110
Current RD+ abcdei fghj 110001 0110 001010 0110 101001 0110 011001 0110 000111 0110 000110 0110 100101 0110 010101 0110 110100 0110 001101 0110 101100 0110 011100 0110 101000 0110 100100 0110 100011 0110 010011 0110 110010 0110 001011 0110 101010 0110 011010 0110 000101 0110 001100 0110 100110 0110 010110 0110 001001 0110 001110 0110 010001 0110 100001 0110 010100 0110
Data Name D3.7 D4.7 D5.7 D6.7 D7.7 D8.7 D9.7 D10.7 D11.7 D12.7 D13.7 D14.7 D15.7 D16.7 D17.7 D18.7 D19.7 D20.7 D21.7 D22.7 D23.7 D24.7 D25.7 D26.7 D27.7 D28.7 D29.7 D30.7 D31.7
Data Value
HGF EDCBA
Current RDabcdei fghj 110001 1110 110101 0001 101001 1110 011001 1110 111000 1110 111001 0001 100101 1110 010101 1110 110100 1110 001101 1110 101100 1110 011100 1110 010111 0001 011011 0001 100011 0111 010011 0111 110010 1110 001011 0111 101010 1110 011010 1110 111010 0001 110011 0001 100110 1110 010110 1110 110110 0001 001110 1110 101110 0001 011110 0001 101011 0001
Current RD+ abcdei fghj 110001 0001 001010 1110 101001 0001 011001 0001 000111 0001 000110 1110 100101 0001 010101 0001 110100 1000 001101 0001 101100 1000 011100 1000 101000 1110 100100 1110 100011 0001 010011 0001 110010 0001 001011 0001 101010 0001 011010 0001 000101 1110 001100 1110 100110 0001 010110 0001 001001 1110 001110 0001 010001 1110 100001 1110 010100 1110
110 00011 110 00100 110 00101 110 00110 110 00111 110 01000 110 01001 110 01010 110 01011 110 01100 110 01101 110 01110 110 01111 110 10000 110 10001 110 10010 110 10011 110 10100 110 10101 110 10110 110 10111 110 11000 110 11001 110 11010 110 11011 110 11100 110 11101 110 11110 110 11111
111 00011 111 00100 111 00101 111 00110 111 00111 111 01000 111 01001 111 01010 111 01011 111 01100 111 01101 111 01110 111 01111 111 10000 111 10001 111 10010 111 10011 111 10100 111 10101 111 10110 111 10111 111 11000 111 11001 111 11010 111 11011 111 11100 111 11101 111 11110 111 11111
MOTOROLA
Appendix B. 8B/10B Coding Scheme
B-7
Data Tables
Table B-3 displays the full valid special character 8B/10B codes.
Table B-3. Valid Special Characters
Name K28.0 K28.1 K28.2 K28.3 K28.4 K28.5 Data Value
HGF EDCBA
Current RDabcdei fghj 001111 0100 001111 1001 001111 0101 001111 0011 001111 0010 001111 1010
Current RD+ abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101
Name K28.6 K28.7 K23.7 K27.7 K29.7 K30.7
Data Value
HGF EDCBA
Current RDabcdei fghj 001111 0110 001111 1000 111010 1000 110110 1000 101110 1000 011110 1000
Current RD+ abcdie fghj 110000 1001 110000 0111 000101 0111 001001 0111 010001 0111 100001 0111
000 11100 001 11100 010 11100 011 11100 100 11100 101 11100
110 11100 111 11100 111 10111 111 11011 111 11101 111 11110
B-8
MC92600 SERDES User's Manual
MOTOROLA
Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. Some of the terms and definitions included in the glossary are reprinted from IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright (c)1985 by the Institute of Electrical and Electronics Engineers, Inc., with the permission of the IEEE.
A B
Asserted. Indicates active state of signal has been set. Refers to either inputs or outputs. BERC. Bit Error Rate Checking. BERT. Bit Error Rate Testing. BIST. Built-In Self-Test. Bit alignment. Refers to the transition tracking loop recovering data bits from the serial input stream. Byte. Eight bits of uncoded data. Byte alignment. Receiver identification of character boundaries through use of Idle character recognition.
C G
Character. An 8B/10B encoded byte of data. Gigabit. A unit of speed of data transfer. One gigabit indicates a data throughput of 1 billion bits per second requiring a transfer rate of 1.25 billion symbols per second of 8B/10B encoded data. Gigabaud. A unit of speed of symbol transfer. One gigabaud indicates a data throughput of 800 million bits per second requiring a transfer rate of 1.0 billion symbols per second of 8B/10B encoded data.
I
ISI. Inter Symbol Interference, a distortion caused by the high-frequency loss characteristics of the transmission media.
MOTOROLA
Glossary
Glossary-1
N P R
Negated. Indicates inactive state of signal has been set. Refers to either inputs or outputs. PLL. Phase Locked Loop. PPM. parts per million. Running disparity. The amount of DC imbalance over a history of symbols transmitted over a link. Equal to the difference between the number of one and zero symbols transmitted. Symbol. One piece of information sent across the link; different from a bit in that bit implies data where symbol is encoded data. Word synchronization. Alignment of four or more receivers' data by adjusting for differences in media and systemic delay between them such that data is presented by the receivers in the same grouping as they were transmit.
S W
Glossary-2
MC92600 SERDES User's Manual
MOTOROLA
Index
Numerics
10-bit interface mode, 3-13, 4-4 2.5V electrical characteristics, 6-4 3.3V electrical characteristics, 6-3 4/1 idle sequence, 3-7 8B/10B coding scheme, B-1 encoding sequence of, B-2 notation, B-1 8B/10B decoder, 3-11 8B/10B encoder, 2-7 reference, 3-9 Coded data transmission, 2-6 Conventions, xiii COREGND/PADGND, 7-13 COREVDD, 7-13
D
DC electrical characteristics, 6-1 DDR, 2-4, 2-8, 3-13 DDRE, 2-3, 3-4 Decoupling recommendations, 4-7 Device operations, 2-7, 3-10 Differential delay line, 3-11 Disparity calculating, B-3 errors, 3-11 proper running, 2-5 word alignment, 4-4 Double data rate mode, 2-4, 3-13, 4-5
A
AC electrical characteristics, 6-4 Add/drop idle mode, 4-5 ADIE, 3-4 Alignment byte, 3-5, 4-4 loss, 3-5 modes, 3-4 modes through the repeater, 4-4 word, 2-5, 3-6
E
Error checking by 8B/10B decoder, 3-11 Error codes BIST, 5-3 Receiver, 3-14
B
BIST error codes, 5-3 BIST sequence system test mode, 5-2 BSYNC_0/ BSYNC_1, 3-4 Byte alignment general, 3-5 modes, 3-5 idle realignment and disparity word, 3-6 non-aligned, 3-6 with realignment, 3-5 Byte interface mode, 3-12, 4-4 Byte-aligned with idle realignment and disparity word alignment, 3-6 Byte-aligned with realignment, 3-5
F
Frequency offset, 3-11
H
Half-speed mode, 3-13, 4-5 hardware specifications and characteristics, 6-1 High speed transceiver clock, 2-4, 3-4 HSE, 2-3, 3-3, 3-13
I
Idle character transmission, 2-5 Idle mode, maintaining alignment, 4-5 Idle sequence, 3-7 Input amplifier, 3-10
C
Clock modes recovered, 3-9
MOTOROLA
Index
Index-1
L
LBE, 2-3, 5-1 LBOE, 2-3 Loop back BIST sequence system test mode, 5-3 Loop back data, 2-4, 3-4 Loop back system test, 5-1
M
MC92600 Initialization, 4-1 Packages, 6-1 MEDIA, 2-4
O
Overrun, 3-9 Overrun/underrun, 3-9
P
Package Description, 7-1 Nomenclature and Dimensions, 7-1, 7-4 Parameter Summary, 7-1 Pinout Listing, 7-8 Thermal characteristics, 7-8 PADVDD, 7-13 Phase-locked loop power supply filtering, 4-6 Pinout listing, 7-8 PLL production test, 5-3 PLL_TPA, 7-12 PLLAGND, 7-13 PLLAVDD, 4-6, 7-13 Power supply characteristics, 6-1 requirements, 4-6 Proper running disparity, B-2
RECV_x_9, 3-3 RECV_x_ERR, 3-3 RECV_x_IDLE, 3-3 RECV_x_K, 3-3 RECV_x_RCLK, 3-3 REF_CLK, 2-3, 3-4 Reference clock DDR mode, 3-13 frequency ranges, 3-14 mode, 3-9 settings, 3-14 REPE, 2-3, 3-4 Repeat data, 2-4 repeat_data, 3-4 Repeater mode, 3-13 settings, 4-3 transmission, 2-4 Repeater mode configurations 10-bit interface, 4-4 add/drop idle, 4-5 byte alignment, 4-4 double data rate, 4-5 half-speed, 4-5 recovered clock, 4-5 word synchronization, 4-4 RESET_B, 7-12 RLINK_x_N/ RLINK_x_P, 3-4
S
Signals internal, 2-4, 3-4 receiver, 3-2 transmitter, 2-2, 2-3, 2-4 signals internal, 3-4 transmitter, 2-3, 2-4 Standby mode, 4-3 Start-up sequence, 4-1 Synchronization byte, 3-5 byte loss, 3-5 word, 3-6, 4-4 idle character generation, 2-5 loss, 3-7 operation, 3-7 proper running disparity, 2-5, 3-7 recommended settings, 3-8 types, 3-7
R
RCCE, 3-4 Receiver 8B/10B decoder, 3-11 block diagram, 3-2 input amplifier, 3-10 modes of operation, 3-12 signals, 3-2 receiver error codes, 3-14 Recovered clock, 3-9, 4-5 RECV_n_ERR, 3-14, 5-3 RECV_n_IDLE, 3-14, 5-3 RECV_n_K, 3-14, 5-3 RECV_x_7 through RECV_x_0, 3-3
T
TBI mode 10-bit interface, 3-13 register operation, 2-8 MC92600 SERDES User's Manual MOTOROLA
Index-2
transmitting, 2-6 TBIE, 2-3, 3-3 Test modes BIST sequence system, 5-2 loop back BIST sequence system, 5-3 loop back system, 5-1 PLL production, 5-3 selecting states, 5-1 Transition density, 2-7, B-1 Transition tracking loop and data recovery, 3-11 Transmission characters encoder operation, 2-7 naming, types, B-2 overview, B-1 Transmission data, 2-5, 2-6 Transmit data input register, 2-8 Transmit driver operation, 2-7 Transmitter block diagram, 2-2 control states, 2-5 modes of operation, 2-4, 2-5 signals, 2-2, 2-3, 2-4 types of data, 2-5 transmitter signals, 2-3, 2-4 TST_0, 5-1 TST_0/ TST_1, 3-4 TST_1, 5-1
XMIT_A_IDLE_B, 7-9 XMIT_B_IDLE_B, 7-9 XMIT_C_IDLE_B, 7-10 XMIT_D_IDLE_B, 7-11 XMIT_n_IDLE_B, 2-3 XMIT_n_K, 3-3 XMIT_x_7 throughXMIT_x_0, 2-3 XMIT_x_IDLE_B, 2-3 XMIT_x_K, 2-3 XPADGND, 7-13 XPADVDD, 7-13
U
Uncoded data in 8B/10B coding scheme, B-1 received data, 3-12 transmission, 2-5 Underrun, 3-9
W
Word alignment, 3-6 Word synchronization 4/1 idle sequence, 3-7 disparity-based idle sequence, 3-7 lock, 3-7 method, 3-7 recommended settings, 3-8 repeater mode, 4-4 timing by recovered clock, 3-9 Word synchronization method, 3-7 WSE, 3-3 WSE_GEN, 2-3, 2-6, 3-3
X
XLINK_x_N/ XLINK_x_P, 2-4
MOTOROLA
Index
Index-3
Index-4
MC92600 SERDES User's Manual
MOTOROLA
Introduction
Transmitter Receiver System Design Considerations Test Features Electrical Specifications and Characteristics Package Description
1 2 3 4 5 6 7
Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index
A B GLO IND
1 2 3 4 5 6 7
Introduction
Transmitter Receiver System Design Considerations Test Features Electrical Specifications and Characteristics Package Description
A B GLO IND
Ordering Information 8B/10B Coding Scheme Glossary of Terms and Abbreviations Index

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